Large Format Fabrication a Practical Approach to Low Cost MCM-D

White, G. Edward; Perfecto, Eric; DeMercurio, T.; McHerron, Dale; Redmond, Thomas F.; Norcott, M.

doi:10.1109/icmcm.1994.753534

Cited by 6 publications

(3 citation statements)

References 1 publication

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“…One of the contributing factors for the higher processing costs is the nonavailability of substrate materials in larger dimensions. It is believed that the ability to process thin films on large area panels (at least 300 mm x 300 mm) would give higher leverage to MCM-D suppliers to meet the existing cost requirements [3,4].…”

Section: Introductionmentioning

confidence: 99%

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Low-cost large area processing using small area substrates-a novel multitiled palletization concept for MCM-D thin film process

Bhattacharya

Gardner²,

Qu³

et al. 2000

IEEE Trans. Adv. Packag.

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MCM-D has been the solution for integrated high density packaging due to its superior line resolution and higher I/O density compared to MCM-C and MCM-L technologies. However, the consumer demand for high performance products at reduced costs is ever increasing, and this trend is expected to continue in the 21st Century. In order to find a low-cost solution for future MCM-D packaging, a novel palletization process which incorporates several tiles (alumina or silicon) on a large carrier glass (pallet) has been established in this study. The multi-tiling format provides simultaneous processing of several small tiles onto a re-usable CTE matched carrier glass. The tiles are attached to the glass with a low modulus adhesive that can be released at an elevated temperature (~450 o C). The objective of this study is to develop a multi-tiling process for a 300 mm x 300 mm area that is scalable up to 600 mm x 600 mm format. There are several challenges in realization of the large area palletization approach, such as formulation and qualification of a high temperature reworkable adhesive and minimization of out-of-plane warpage of the tiled assembly. Finite element models for warpage and its validation by Shadow Moire measurement, formulation of a compliant adhesive for thermal stability up to 400 o C are reported in previous publications. This paper deals with (i) the validation of the palletization concept on a 300 mm x 300 mm glass with weight restriction below 3 pounds and thickness limitation to < 6.25 mm, and (ii) qualification of the formulated adhesive through a correlative study on high temperature detachability of the attached tiles, chemical compatibility of the adhesive with acids, bases, and less polar solvents, and interfacial shear strength at the glass/adhesive/tile joints. MCM-D thin film process on the tiled substrates is to be conducted by the member companies of the MCM-D Consortium.

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Section: Introductionmentioning

confidence: 99%

“…Materials that are available in large format (such as organic boards) are not compatible with MCM-D, primarily due to its high temperature process requirements. IBM [3] has demonstrated fabrication of thin films for MCM-D on 300 mm x 300 mm panels by modifying their existing tools and processes.…”

Section: Introductionmentioning

confidence: 99%

Low-cost large area processing using small area substrates-a novel multitiled palletization concept for MCM-D thin film process

Bhattacharya

Gardner²,

Qu³

et al. 2000

IEEE Trans. Adv. Packag.

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“…Process temperatures of the post-IC process should not exceed a certain temperature (normally, in the range of 400-500 • C [12]) so as not to damage or alter the performance of already-fabricated foundry IC. In multichip module deposited (MCM-D) applications [13], interlayer dielectrics separate and insulate metal conductors to form a vertical interconnection structure. Since the physical interlayer structure of the MCM-D is similar to that required for vertically integrated MEMS, a combination of electroplating-based micromachining techniques with MCM-D processing technology could provide the means for realizing a vertically integrated MEMS.…”

Section: Introductionmentioning

confidence: 99%

Planarization techniques for vertically integrated metallic MEMS on silicon foundry circuits

Lee

English

Ahn

et al. 1997

J. Micromech. Microeng.

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Various micromachining techniques exist to realize integrated microelectromechanical systems (MEMS), which include sensors, signal processing and/or driving circuits, and/or actuators in one small die. Post-processing techniques performed on foundry-fabricated circuits (e.g., MOSIS) are attractive since such an approach eliminates the need for an in-house integrated circuit fabrication line to produce integrated MEMS. A method based on the combination of metallic (e.g., electroplating) micromachining techniques with multichip module deposited (MCM-D) processes is a possible candidate to realize vertically-stacked integrated MEMS using the post-processing of integrated circuits (post-IC) approach. In order to realize such devices, planarization of the surface of foundry-fabricated circuit chips or wafers is often required. In such planarization layers, mechanical and chemical stability, as well as adhesion between the circuit-containing substrate and the micromachined devices, should be addressed. A PI/BCB/PI sandwich interlayer system, which utilizes both advantages of DuPont polyimide PI 2611 and Dow benzocyclobutene (BCB) Cyclotene 3022 series, was developed as a planarization interlayer for vertically integrated MEMS. The PI/BCB/PI interlayer system shows an over 95% degree of planarization (DOP) as well as passes the Method 107G Thermal Shock from the military standard MIL-STD-202F. A SiO 2 /BCB/SiO 2 interlayer system was also developed as an alternative to the PI/BCB/PI system.

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