The problems encountered in the observation of large leakage-current reduction of thin SiO 2 due to enhanced phonon-energy coupling were thoroughly analyzed. A lithographic method based on bilayer resists ͑SU-8 and Shipley S1813͒ and an organic developer ͑SU-8 developer͒ was developed to fabricate Ni-gate metal-oxide-semiconductor ͑MOS͒ capacitors. After development, an undercut profile of the bilayer resists was clearly demonstrated. A key step, thorough deionized water rinse after a quick isopropyl alcohol rinse during resist patterning, is critical to obtain well-defined Ni electrodes reproducibly. Experimental currentvoltage and capacitance-voltage ͑C-V͒ curves of the Ni-gate MOS capacitors, together with the C-V curves simulated using the Berkeley Quantum simulator, demonstrate that a large leakage-current reduction ͑ ϳ 100ϫ ͒ can be reliably and reproducibly achieved on thin SiO 2 ͑ ϳ 23 Å͒ after proper rapid thermal processing.Complimentary metal oxide semiconductor ͑CMOS͒ technology needs thin gate silicon oxide dielectrics for metal-oxidesemiconductor ͑MOS͒ transistors ͑ Ͻ 15 Å͒. However, the gate leakage current increases exponentially as the gate dielectrics are further scaled down due to direct quantum tunneling. Currently, the industry uses alternative high permittivity ͑high-k͒ gate dielectrics such as HfO 2 and HfSiON to solve the gate leakage problem. However, an interfacial SiO 2 layer ͑4-6 Å͒ between the high-k dielectric and Si is necessary to maintain a good interface. Therefore, any improvement of leakage current of SiO 2 is very helpful to MOS transistors.Recently, phonon-energy-coupling enhancement ͑PECE͒ was discovered. 1-5 Surprisingly, this leads to a reduction of quantum tunneling current of SiO 2 by 2-5 orders of magnitude. 1-5 Because of the nature of the phonon coupling, any attack of the SiO 2 structure by chemicals and plasmas may result in a partial loss of the PECE effect. 3 Alkaline-based chemicals and plasmas must be avoided, including regular photoresist ͑PR͒ developer and sputtering deposition. In the past, we patterned Al gate metal by the evaporation of Al through shadow masks. 1-4 This may produce unreliable results because the area of MOS capacitors varies during evaporation through shadow masks at different angles across a large substrate. It was strongly suggested by researchers in industry that only both currentvoltage ͑I-V͒ and capacitance-voltage ͑C-V͒ curves from the same device fabricated using a lithographic method are required to validate the observed effect. 6 For aggressively scaled CMOS logic devices, the industry uses a high-k gate oxide stack, which consists of a chemical oxide ͑SiO 2 ͒ interfacial layer of ϳ0.7 nm and an atomic layer deposited HfO 2 film of 1.8-2.0 nm ͓equivalent oxide thickness ͑EOT͒ = ϳ 0.3 nm͔. 7 The scaling is achieved by thinning the chemical oxide while the thickness of HfO 2 remains the same at 1.8-2.0 nm. If the PECE effect can be applied to the high-k gate stack, both the chemical oxide and HfO 2 can be scaled down while the leakag...