“…MUX: z = a 0 s 1 s 0 + a 1 s 1 s 0 + a 2 s 1 s 0 + a 3 s 1 s 0 γ 1 : ι γ 2 : (a 0 , a 2 )(a 0 , a 2 )(a 1 , a 3 )(a 1 , a 3 )(s 1 , s 1 ) γ 3 : (a 1 , a 2 )(a 1 , a 2 )(s 0 , s 1 )(s 0 , s 1 ) γ 4 : (a 0 , a 1 , a 3 , a 2 )(a 0 , a 1 , a 3 , a 2 )(s 0 , s 1 , s 0 , s 1 ) γ 5 : (a 0 , a 1 )(a 0 , a 1 )(a 2 , a 3 )(a 2 , a 3 )(s 0 , s 0 ) γ 6 : (a 0 , a 3 )(a 0 , a 3 )(a 1 , a 2 )(a 1 , a 2 )(s 0 , s 0 )(s 1 , s 1 ) γ 7 : (a 0 , a 2 , a 3 , a 1 )(a 0 , a 2 , a 3 , a 1 )(s 0 , s 1 , s 0 , s 1 ) γ 8 : (a 0 , a 3 )(a 0 , a 3 )(s 0 , s 1 )(s 0 , s 1 ) γ 9 : (a 0 , a 0 )(a 1 , a 1 )(a 2 , a 2 )(a 3 , a 3 )(z, z ) γ 10 : (a 0 , a 2 )(a 0 , a 2 )(a 1 , a 3 )(a 1 , a 3 )(s 1 , s 1 )(z, z ) γ 11 : (a 0 , a 0 )(a 1 , a 2 )(a 1 , a 2 )(a 3 , a 3 )(s 0 , s 1 )(s 0 , s 1 )(z, z ) γ 12 : (a 0 , a 1 , a 3 , a 2 )(a 0 , a 1 , a 3 , a 2 )(s 0 , s 1 , s 0 , s 1 )(z, z ) γ 13 : (a 0 , a 1 )(a 0 , a 1 )(a 2 , a 3 )(a 2 , a 3 )(s 0 , s 0 )(z, z ) γ 14 : (a 0 , a 3 )(a 0 , a 3 )(a 1 , a 2 )(a 1 , a 2 )(s 0 , s 0 )(s 1 , s 1 )(z, z ) Generating Set: g = {γ 3 , γ 5 , γ 9 } inputs and outputs is investigated [1], [2]. Other applications include BDD minimization [3] and circuit power optimization [4].…”