Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems

Whang, Dongmok; Jin, Song; Wu, and Yue; Lieber, Charles M.

doi:10.1021/nl0345062

Cited by 826 publications

(648 citation statements)

References 20 publications

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“…This method opens a unique avenue to integrate high-κ dielectrics on graphene with the preservation of high carrier mobility. With further optimization of nanoribbon growth and assembly process to precisely control their physical dimension and spatial location (36)(37)(38)(39)(40), large arrays of top-gated graphene transistors or circuits can be envisioned. This physical assembly and integration approach can thus open a unique avenue to high-performance graphene electronics to impact broadly from high frequency high speed circuits to flexible electronics.…”

Section: Discussionmentioning

confidence: 99%

High- κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

Liao¹,

Bai

Qu³

et al. 2010

Proc. Natl. Acad. Sci. U.S.A.

194

158

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Deposition of high-κ dielectrics onto graphene is of significant challenge due to the difficulties of nucleating high quality oxide on pristine graphene without introducing defects into the monolayer of carbon lattice. Previous efforts to deposit high-κ dielectrics on graphene often resulted in significant degradation in carrier mobility. Here we report an entirely new strategy to integrate high quality high-κ dielectrics with graphene by first synthesizing freestanding high-κ oxide nanoribbons at high temperature and then transferring them onto graphene at room temperature. We show that single crystalline Al 2 O 3 nanoribbons can be synthesized with excellent dielectric properties. Using such nanoribbons as the gate dielectrics, we have demonstrated top-gated graphene transistors with the highest carrier mobility (up to 23,600 cm 2 ∕V · s) reported to date, and a more than 10-fold increase in transconductance compared to the back-gated devices. This method opens a new avenue to integrate high-κ dielectrics on graphene with the preservation of the pristine nature of graphene and high carrier mobility, representing an important step forward to high-performance graphene electronics.graphene dielectric integration | carrier mobility | dielectric nanoribbon | nanoelectronics G raphene has attracted considerable interest as a potential electronic material due to its exceptionally high carrier mobility and tunable band gap (1-6). Various strategies have been explored to fabricate field-effect transistors based on graphene or graphene nanostructures (6-13). Most of these efforts to date employ a silicon substrate as a global back gate and silicon oxide as the gate dielectric, which have led to many interesting scientific discoveries, but will be of limited use for practical applications due to the high-gate switching voltage required and the inability to independently address individual devices on the same chip. Top-gated devices with high-κ dielectrics can significantly reduce the required switching voltage and readily allow independently addressable device arrays and functional circuits, and therefore are of significant interest (14, 15).The gate dielectric is an essential component of a transistor, which can significantly impact the critical device parameters including transconductance, subthreshold swing and frequency response. Exploring graphene for future electronics requires effective integration of high quality gate dielectrics, in particular the high-κ dielectrics. However, it has been rather challenging to deposit oxide dielectrics onto graphene without introducing defects. The deposition of high-κ dielectrics is usually achieved using atomic layer deposition (ALD), which requires reactive surface groups (16)(17)(18)(19)(20). Functionalization of graphene surface for ALD either introduces undesired impurities or breaks the chemical bonds in the graphene lattice, inevitably leading to a significant degradation in carrier mobilities (20). Physical vapor deposition (PVD) such as electron-beam evaporation or sput...

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Section: Discussionmentioning

confidence: 99%

High- κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

Liao¹,

Bai

Qu³

et al. 2010

Proc. Natl. Acad. Sci. U.S.A.

194

158

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“…Specifically, the bit size in the crossbar structure is defined by the diameters of the orthogonal nanoscale wires, the electronic characteristics of the functional element are defined by the two crossed wires (for example, coaxial core-shell materials), and the device density is governed by the density at which the CNTs and nanowires are assembled. This architecture is also attractive owing to its simplicity and the fact that scalable bottom-up techniques have already yielded 2D meshes of chemically synthesized nanowires [9][10][11] , CNTs 12 and molecular devices 13,14 .…”

Section: Nanoscale Memory Architecturementioning

confidence: 99%

Nanoelectronics from the bottom up

2007

Self Cite

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“…The other is Langmuir-Blodgett technique, relying on the uniaxial compression of a NW-surfactant monolayer on an aqueous phase to produce the aligned ordered NWs [19], [20], [21]. By repeating these sequent steps, cross and more complex NW structure can be built with the controlled orientation for more integrated devices.…”

Section: Nanowire Manipulation Assembly and Contactmentioning

confidence: 99%

In-Fiber Semiconductor Filament Arrays

et al. 2008

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One-dimensional nanostructures with high aspect-ratios and nanometer cross-sectional dimensions have been the focus of recent studies in the persistent drive to miniaturize devices. Conventional bottom-up methods such as vapor-liquid-solid growth have been widely applied for the fabrication of uniform and high quality nanowires. Two challenges toward nanoelectronics and other applications remain: on the singlenanowire level, precisely manipulating an individual nanowire for the sophisticated functionalities, and on the multiple-nanowire level, integrating nanowires into designed architecture at large scale. Thus, an alternative approach with the capacity to achieve ordered and extended nanowires is highly desirable.In this thesis, we observe an intriguing phenomenon that a cylindrical shell upon reaching a characteristic thickness breaks up into filament arrays during optical-fiber thermal drawing. This structural evolution occurs exclusively in the cross-sectional plane, while the uniformity along the axial direction remains intact. We demonstrate crystalline semiconductor nanowires by post-drawing annealing procedure and characterize their electrical and optoelectric properties for the devices such as optical switch. This top-down thermal drawing approach provides new opportunities for nanostructure fabrication with high throughput and at low cost, and offers promising applications in renewable energy and data storage.In order to understand the stability (or instability) of thin shells and filaments, we explore a physical mechanism during the complicated thermal drawing. A perspective of capillary instability from fluid mechanics is focused. Axial stability of continuous filaments is consistent with capillary instability. Axial stability of a thicker cylindrical shell arises from large radius and high viscosity. These results provide theoretical guidance in the understanding of attainable feature sizes and in materials selection to expand the potential functionalities of devices in microstructured fibers.

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Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems

Cited by 826 publications

References 20 publications

High- κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

High- κ oxide nanoribbons as gate dielectrics for high mobility top-gated graphene transistors

Nanoelectronics from the bottom up

In-Fiber Semiconductor Filament Arrays

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