Flip chip packaging as a mainstream packaging interconnect technology has proliferated rapidly within the last decade or so. With the applications of high-performance chip, its thickness and size have been much thinner and bigger, which is challenging the current assembly technique, especially for the reliable peeling of ultrathin die from the wafer due to its vulnerability and flexibility. Here, we present some significant analytical formulas to estimate die cracking stress and peeling energy in die peeling process. The effects of two factors, including peeling cracking propagation and ejecting needle configuration, are investigated using a fracture mechanics framework. Meanwhile, all analytical predictions have been verified via finite element modeling with virtual crack technique. Theoretical results have shown that die cracking stress could be effectively reduced, but it rarely works to improve peeling energy when more needles are embedded below the adhesive tape. In particular, the essence of the technique with the multineedle is discussed, compared with the normal single-needle technique, which can be used to guide the design of ultrathin die peeling process.Index Terms-Adhesive layer, chip peeling-off, die-cracking stress, energy release rate (ERR), microelectronic packaging, multineedle ejector.