Laser Processing For 3D Junctionless Transistor Fabrication

Abstract

To take fully advantage of Junctionless transistor (JLT) low cost and low temperature feature we investigate a 475°C process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 10 19 at/cm 3) poly-silicon film featuring excellent roughness values (R max = 1.6nm and RMS=0.2nm). Guidelines for grain size optimization with nanosecond (ns) laser annealing are given.