Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA

Kastensmidt, Fernanda Lima; Tambara, Lucas Antunes; Bobrovsky, Dmitry V.; Pechenkin, Alexander; Nikiforov, Alexander Y.

doi:10.1109/tns.2014.2369008

Cited by 27 publications

(6 citation statements)

References 19 publications

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“…Pulsed laser systems have been widely used in SEE research for SRAMs [16,17]. The size of a single SRAM cell is always in the range of one micron with modern technologies.…”

Section: Sensitivity Mapping For Regula_11t Sram Structurementioning

confidence: 99%

Developing a Universal Mirror–mirror Laser Mapping System for Single Event Effect Research

Belev

Tian

et al. 2020

Applied Sciences

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Research on single event effects (SEEs) is significant to the design and manufacture of modern electronic devices. By applying two photon absorption (TPA) ultra-fast pulsed lasers, extra electron-hole pairs (EHPs) are generated in a desired location on a chip, simulating the process that could occur in the circuit by energetic particles. In this study, a SEE sensitivity mapping system is described which uses this method to generate real-time sensitivity maps for various electronic devices. The system hardware includes an attenuator to control the energy, a Pockels cell as a fast-optical switcher and a mirror–mirror module to project the laser beam into a certain location. The system software developed for this application controls the laser system, automatically generates sensitivity maps, communicates with the testing devices and logs the SEE results. The two main features of this laser mapping system are: high scanning velocity for large area scanning (about 1 × 1 mm) and high spatial resolution for small area scanning (about 1 × 1 μm). To verify this mapping system, sensitivity maps were generated for static random access memory (SRAM) built with 65 nm technology and for commercial operational amplifiers (op-amps). The achieved sensitivity maps were compared with circuitry analysis and laser testing results, confirming this mapping system to be effective.

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“…Pulsed laser systems have been widely used in SEE research for SRAMs [16,17]. The size of a single SRAM cell is always in the range of one micron with modern technologies.…”

Section: Sensitivity Mapping For Regula_11t Sram Structurementioning

confidence: 99%

Developing a Universal Mirror–mirror Laser Mapping System for Single Event Effect Research

Belev

Tian

et al. 2020

Applied Sciences

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“…SET effects modeling in different types of asynchronous logic elements combinations are presented in [6] - [9]. The presented data analysis makes it possible to conclude that authors use two basic combinationsparallel ( Fig.…”

Section: Typical Schemes Of Sets Effects Research In Digital Icsmentioning

confidence: 99%

Single event transients monitoring and diagnostic in FPGA

Sorokoumov

2018

FACTA U EE

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Analysis of single event transients (SETs) generated in field programmable gate arrays (FPGA) under heavy charged particles (HCP) irradiation and SET suppression methods is performed. The circuit for FPGA SET detection is designed for transients generated both inside FPGA and outside at package pin level. SET registration inside FPGA is carried out as an event when logical cell is switched. The SET control schematic circuit efficiency has been comparatively verified using heavy ion accelerator and picosecond focused laser source. SET in FPGA experimental results are presented and discussed.

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“…The faults are typically found and analyzed by a readback of the bitstream from the device after each fault injection to be compared with the unaffected golden sample [2,20], in order to figure out the affected tiles on the logic array. The comparison efficiency is low and static, and furthermore, the method is becoming challenging to apply to newer FPGAs with more obscure bitstream formats.…”

Section: Related Workmentioning

confidence: 99%

Extensive Laser Fault Injection Profiling of 65 nm FPGA

Breier

He²,

Bhasin

et al. 2017

J Hardw Syst Secur

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Fault injection attacks have been widely investigated in both academia and industry during the past decade. In this attack approach, the adversary intentionally induces This paper is an extension of the paper entitled "Comprehensive Laser Sensitivity Profiling and Data Register Bit-Flips for Cryptographic Fault Attacks in 65 nm FPGA," presented at SPACE'16 conference. This version contains an extended related work, covers chip preparation in more details, discusses compatibility with cryptographic fault injection attacks, and presents a countermeasure against laser profiling. computational faults in the security components of the integrated circuit (IC) for deducing the confidential information processed or stored inside the device. However, the internal architecture of real-world devices is typically unknown to the attacker and the insufficient information about the device internals often cannot satisfy requirements of a practical fault injection attack. In this paper, we target Field Programmable Gate Array (FPGA) that is widely used in hardware security applications. By analyzing the faulty outputs of implemented algorithms, the scale of logic arrays and the sensitive logic cells can be precisely profiled. Using the outcome of this work, practical attacks can be significantly accelerated, without a need of time-consuming chip-scale injection scan. In addition, the observed fault models are compatible with most of the previously proposed fault models for differential or algebraic fault attacks (DFA/AFA). Moreover, a low-cost and highly sensitive logic-level countermeasure for predicting the laser fault injection attempt is described, which can be applied into any digital IC with a minimal overhead. Jakub

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Laser Testing Methodology for Diagnosing Diverse Soft Errors in a Nanoscale SRAM-Based FPGA

Cited by 27 publications

References 19 publications

Developing a Universal Mirror–mirror Laser Mapping System for Single Event Effect Research

Developing a Universal Mirror–mirror Laser Mapping System for Single Event Effect Research

Single event transients monitoring and diagnostic in FPGA

Extensive Laser Fault Injection Profiling of 65 nm FPGA

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