Laser thermal anneal of polysilicon channel to boost 3D memory performance

Nanoscaled Electrical Characterization

“…A buried array of vertical poly-Si channels (pillar) is used. These structures are originally deposited as vertical gate for 3D NAND application and their fabrication process can be found elsewhere [48]. The height of the pillar is 200 nm with a 80 nm diameter, they are grown to form an array structure with 500 nm pitch between neighbor pillars.…”

3D NAND Flash Architectures

“…To compensate the enlarged string resistance, channel mobility enhancement is critically important. Laser annealing process was demonstrated to boost the poly-silicon channel mobility (Lisoni et al 2014). However, the limitation of laser penetration depth is concerned.…”

Individual analysis of inter and intragrain defects in electrically characterized polycrystalline silicon nanowire TFTs by multicomponent dark-field imaging based on nanobeam electron diffraction two-dimensional mapping

“…7) For such poly-Si NW TFTs with a gate size smaller than the mean grain size of poly-Si, it is considered that the variation in the number of grain boundaries (GBs) inside channels induces characteristic variations. 6,[8][9][10][11][12] In addition, it has been reported that intragrain defects, such as dislocations and lattice distortions, degrade the characteristics of TFTs as well as GBs. 7,13) To elucidate the factor of characteristic variations, we investigate the channel crystallinities of the electrically characterized individual NW TFTs.…”