Latch-Based Logic Locking

Sweeney, Joseph; Zackriya, V. Mohammed; Pagliarini, Samuel; Pileggi, Lawrence T.

doi:10.1109/host45689.2020.9300256

Cited by 28 publications

(5 citation statements)

References 26 publications

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“…For the obfuscation of DSP circuits, a novel approach that uses high-level transformations, a key-based finite-state machine and a reconfigurator was introduced in [30]. The use of decoys in obfuscation has been utilized in [31], but in a manner that is not related to the IP itself, as the decoys are keyed gates. To make the reverse engineering of coefficients of an FIR filter harder for an enduser, adding input and output noises was proposed in [32].…”

Section: Related Workmentioning

confidence: 99%

High-level Intellectual Property Obfuscation via Decoy Constants

Aksoy¹,

Nguyen²,

Almeida³

et al. 2021

Preprint

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This paper presents a high-level circuit obfuscation technique to prevent the theft of intellectual property (IP) of integrated circuits. In particular, our technique protects a class of circuits that relies on constant multiplications, such as filters and neural networks, where the constants themselves are the IP to be protected. By making use of decoy constants and a key-based scheme, a reverse engineer adversary at an untrusted foundry is rendered incapable of discerning true constants from decoy constants. The time-multiplexed constant multiplication (TMCM) block of such circuits, which realizes the multiplication of an input variable by a constant at a time, is considered as our case study for obfuscation. Furthermore, two TMCM design architectures are taken into account; an implementation using a multiplier and a multiplierless shift-adds implementation. Optimization methods are also applied to reduce the hardware complexity of these architectures. The well-known satisfiability (SAT) and automatic test pattern generation (ATPG) attacks are used to determine the vulnerability of the obfuscated designs. It is observed that the proposed technique incurs small overheads in area, power, and delay that are comparable to the hardware complexity of prominent logic locking methods. Yet, the advantage of our approach is in the insight that constants -instead of arbitrary circuit nodes -become key-protected.

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Section: Related Workmentioning

confidence: 99%

High-level Intellectual Property Obfuscation via Decoy Constants

Aksoy¹,

Nguyen²,

Almeida³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

“…Countermeasures to secure an IC also apply to a malicious end-user that can be interested in reverse engineering a design. Noteworthy examples of countermeasures are Logic Locking [6]- [10], IC Camouflaging [11]- [13], Split Manufacturing [14], [15], and FPGA-like obfuscation approaches [16]- [24]. The latter style of obfuscation attempts to exploit an FPGA (or FPGA-like) fabric, where the functionality of the circuit is hidden by the configuration and the bitstream serves as a key to unlock the design.…”

Section: Introductionmentioning

confidence: 99%

A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs

Abideen

Perez

Martins

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Numerous threats are associated with the globalized integrated circuit (IC) supply chain, such as piracy, reverse engineering, overproduction, and malicious logic insertion. Many obfuscation approaches have been proposed to mitigate these threats by preventing an adversary from fully understanding the IC (or parts of it). The use of reconfigurable elements inside an IC is a known obfuscation technique, either as a coarse grain reconfigurable block (i.e., eFPGA) or as a fine grain element (i.e., FPGA-like look-up tables). This paper presents a securityaware CAD flow that is LUT-based yet still compatible with the standard cell based physical synthesis flow. More precisely, our CAD flow explores the FPGA-ASIC design space and produces heavily obfuscated designs where only small portions of the logic resemble an ASIC. Therefore, we term this specialized solution a "hybrid ASIC" (hASIC). Nevertheless, even for heavily LUT-dominated designs, our proposed decomposition and pin swapping algorithms allow for performance gains that enable performance levels that only ASICs would otherwise achieve. On the security side, we have developed novel template-based attacks and also applied existing attacks, both oracle-free and oraclebased. Our security analysis revealed that the obfuscation rate for an SHA-256 study case should be at least 45% for withstanding traditional attacks and at least 80% for withstanding templatebased attacks. When the 80% obfuscated SHA-256 design is physically implemented, it achieves a remarkable frequency of 368MHz in a 65nm commercial technology, whereas its FPGA implementation (in a superior technology) achieves only 77MHz.

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“…Alongside the continuous miniaturization trend that ICs have benefited from for decades, new security threats have emerged and are now frequently studied. Among them, the theft of intellectual property (IP) has been the target of many studies [4,5,7,9,10,11,12].…”

Section: Introductionmentioning

confidence: 99%

“…Approaches anchored on partial trusted fabrication have been proposed [9] but have not been adopted by the industry. Logic locking [10] studies have received a fair amount of attention and many derivatives of the original concept have emerged [12]. However, powerful attacks against logic locking are continuously proposed.…”

Section: Introductionmentioning

confidence: 99%

Obfuscating the Hierarchy of a Digital IP

Basiashvili¹,

Abideen²,

Pagliarini³

2022

Preprint

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Numerous security threats are emerging from untrusted players in the integrated circuit (IC) ecosystem. Among them, reverse engineering practices with the intent to counterfeit, overproduce, or modify an IC are worrying. In recent years, various techniques have been proposed to mitigate the aforementioned threats but no technique seems to be adequate to hide the hierarchy of a design. Such ability to obfuscate the hierarchy is particularly important for designs that contain repeated modules. In this paper, we propose a novel way to obfuscate such designs by leveraging conventional logic synthesis. We exploit multiple optimizations that are available in the synthesis tool to create design diversity. Our security analysis, performed by using the DANA reverse engineering tool, confirms the significant impact of these optimizations on obfuscation. Among the many considered obfuscated design instances, users can find options that incur very small overheads while still confusing the work of a reverse engineer.

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Latch-Based Logic Locking

Cited by 28 publications

References 26 publications

High-level Intellectual Property Obfuscation via Decoy Constants

High-level Intellectual Property Obfuscation via Decoy Constants

A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs

Obfuscating the Hierarchy of a Digital IP

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