Latch-Controlled Current Cell for Low Power Current-Steering D/A Converter

Lee, Chan-Soo; Park, Jung-Woong; Lee, Hyung-Gyoo; Kim, Nam-Soo; Jin, Hai-Feng

doi:10.1109/uksim.2012.100

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2015

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“…Its ability is contributing by an array of matched current sources. [15] Several architectures in the current steering are two stage, interpolatedand segmentation [16]- [18]. Interpolating DACs use a pulse density conversion technique that allows for the use of a lower resolution DAC internally.…”

Section: Introductionmentioning

confidence: 99%

Low Power Designs of Current Steered DACs in CMOS Process: A Review

Mazlanna

Mazlan

Jalil

et al. 2015

ijeei

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Low power design has become popular nowadays because ofdevelopment of improveddata converters with high resolution in CMOS process. Electronic device manufacturersare competing each other to produce devices that can extend battery life, have inexpensive packaging and cooling systems as well as reduce the size.The objective of this paper is to review various low power designs in digital to analog converters (DAC). The methods used to reduce the power consumption are presented in details. We focused the designs in the segmentation current steering DACs, as most of the low power designs illustarted in literatures are based on this architecture. From this review, we find that triple segmented architectureand spike free switching can reduce the power consumption effectively. This review paper can be a reference for the researchers and engineers to develop low power CMOS DACsfor various applications.

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Section: Introductionmentioning

confidence: 99%