Latency and Power Measurements on a 64-kb Hybrid Josephson-CMOS Memory

Liu, Q.; Fujiwara, K.; Meng, Xiaofan; Whiteley, S.R.; Duzer, T. Van; Yoshikawa, Nobuyuki; Thakahashi, Y.; Hikida, Toshihide; Kawai, Nobuhiro

doi:10.1109/tasc.2007.898698

Cited by 18 publications

(11 citation statements)

References 10 publications

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“…In order to get around the low capacity of superconductor memories, hybrid superconductor-semiconductor schemes were pursued combining room-temperature CMOS memory and RSFQ interface circuits [26] or building a cryogenic (4 K) hybrid Josephson junction (JJ) CMOS RAM [27]. Recently, a cryogenic 64 kbit hybrid JJ-CMOS RAM was successfully demonstrated [28].…”

Section: Introductionmentioning

confidence: 99%

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Vernik

Bolginov

Bakurskiy

et al. 2013

IEEE Trans. Appl. Supercond.

146

105

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We investigate a Magnetic Josephson Junction (MJJ) -a superconducting device with ferromagnetic barrier for a scalable high-density cryogenic memory compatible with energyefficient single flux quantum (SFQ) circuits. The superconductorinsulator-superconductor-ferromagnet-superconductor (SIS FS) MJJs are analyzed both experimentally and theoretically. We found that the properties of SIS FS junctions fall into two distinct classes based on the thickness of S layer. We fabricate Nb-Al/AlOx-Nb-PdFe-Nb SIS FS MJJs using a co-processing approach with a combination of HYPRES and ISSP fabrication processes. The resultant SIS FS structure with thin superconducting S -layer is substantially affected by the ferromagnetic layer as a whole. We fabricate these type of junctions to reach the device compatibility with conventional SIS junctions used for superconducting SFQ electronics to ensure a seamless integration of MJJ-based circuits and SIS JJ-based ultra-fast digital SFQ circuits. We report experimental results for MJJs, demonstrating their applicability for superconducting memory and digital circuits. These MJJs exhibit I c R n product only ∼30% lower than that of conventional SIS junctions co-produced in the same fabrication. Analytical calculations for these SIS FS structures are in a good agreement with the experiment. We discuss application of MJJ devices for memory and programmable logic circuits.Index Terms-Energy efficient, memory devices, proximity effect, RAM, single flux quantum, superconducting logic elements.

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Section: Introductionmentioning

confidence: 99%

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Vernik

Bolginov

Bakurskiy

et al. 2013

IEEE Trans. Appl. Supercond.

146

105

View full text Add to dashboard Cite

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“…Since superconducting SFQ memories do not have large capacity [6] and cryogenic hybrid Josephson-CMOS memories are not yet available [7], we pursue a hybrid temperature-hybrid technology approach [2]. In this approach, we integrate a large capacity room-temperature semiconductor memory and a fast cryogenic RSFQ cache integrated on the same chip with an RSFQ digital signal processor.…”

Section: A Hybrid Memory Configurationmentioning

confidence: 99%

Hybrid Semiconductor-Superconductor Fast-Readout Memory for Digital RF Receivers

Mukhanov

Kirichenko

Filippov

et al. 2011

IEEE Trans. Appl. Supercond.

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Results of the development of a new type of a hybrid memory for superconducting Digital-RF receivers supporting 30 Gbps memory readout speed are presented. The main feature of this memory is a combination of a high capacity room-temperature memory and a high speed on-chip superconductive cache in order to provide digital waveform templates for Digital-RF signal processing. As a room-temperature high-capacity memory with fast readout, we selected Sympuls pattern generator BMG 30 G-64 M capable of producing a 30 Gbps serial data stream of programmable pattern of 67,108,864 bits. We designed, fabricated, and tested an on-chip cache which receives high-speed template serial data from the room temperature memory and converts it into a stream of 3-bit words of template of local oscillator (LO) for digital mixer. We integrated the memory with a 1 3-bit digital I/Q mixer (1-bit digitized RF stream multiplied by 3-bit digital LO).

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“…Cryogenic memory plays an important role in the development of superconducting-based computing. A variety of designs have been proposed including memories based on single flux quantum (SFQ) digital logic [3], hybrid superconducting-CMOS designs [4,5], magnetic random access memory (RAMs) [6], and others [7]. Some of the main challenges in developing superconducting memory are reducing power dissipation, increasing access speed, and reducing the size of the chip [7].…”

Section: Introductionmentioning

confidence: 99%

Parameter optimization for transitions between memory states in small arrays of Josephson junctions

Rezac

Imam

Braiman

2017

Physica A: Statistical Mechanics and its Applications

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Coupled arrays of Josephson junctions possess multiple stable zero voltage states. Such states can store information and consequently can be utilized for cryogenic memory applications. Basic memory operations can be implemented by sending a pulse to one of the junctions and studying transitions between the states. In order to be suitable for memory operations, such transitions between the states have to be fast and energy efficient. In this paper we employed simulated annealing, a stochastic optimization algorithm, to study parameter optimization of array parameters which minimizes times and energies of transitions between specifically chosen states that can be utilized for memory operations (Read, Write, and Reset). Simulation results show that such transitions occur with access times on the order of 30 -100 ps and access energies on the order of 10 -19 -5  10 -18 J. Numerical simulations are validated with approximate analytical results. 05.45.Xt, 85.25.Cp, 85.25.Hv Recently we introduced a simple memory paradigm based on the existence of multiple stable states present in a large variety of nonlinear systems [8,9]. The transitions between those states act as basic memory cell operations (Write, Read, and Reset). The paradigm presented in references 8 and 9 is

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Latency and Power Measurements on a 64-kb Hybrid Josephson-CMOS Memory

Cited by 18 publications

References 10 publications

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Magnetic Josephson Junctions With Superconducting Interlayer for Cryogenic Memory

Hybrid Semiconductor-Superconductor Fast-Readout Memory for Digital RF Receivers

Parameter optimization for transitions between memory states in small arrays of Josephson junctions

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