Latency-driven design for FPGA-based convolutional neural networks

Venieris, Stylianos I.; Bouganis, Christos-Savvas

doi:10.23919/fpl.2017.8056828

Cited by 80 publications

(56 citation statements)

References 16 publications

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“…mean) in the error tolerance range of 1 to 5%. In the same error range, Cas-cacdeCNN also outperforms the works of [20] and [30] by up to 8.29× and 24.83× respectively. Similarly for VGG-16, the full cascade architecture outperforms the mixed OpenCL-RTL design of [29] by up to 2.73× with an average of 2.36× (geo.…”

Section: Comparison With Existing Fpga Workmentioning

confidence: 87%

Cascade^CNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks

Kouris

Venieris

Bouganis

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

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This work presents CascadeCNN, an automated toolflow that pushes the quantisation limits of any given CNN model, aiming to perform high-throughput inference. A two-stage architecture tailored for any given CNN-FPGA pair is generated, consisting of a low-and high-precision unit in a cascade. A confidence evaluation unit is employed to identify misclassified cases from the excessively low-precision unit and forward them to the high-precision unit for re-processing. Experiments demonstrate that the proposed toolflow can achieve a performance boost up to 55% for VGG-16 and 48% for AlexNet over the baseline design for the same resource budget and accuracy, without the need of retraining the model or accessing the training data.

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Section: Comparison With Existing Fpga Workmentioning

confidence: 87%

Cascade^CNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks

Kouris

Venieris

Bouganis

2018

2018 28th International Conference on Field Programmable Logic and Applications (FPL)

Self Cite

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“…We also like to acknowledge Dr. Blair P. Bremberg and Ms. Sumaiya Hussain Sadiq for their help in professional English editing of this manuscript. VOLUME 4, 2018 NeuFlow [143] Memory-Centric Accelerator [146] nn-X [148] Roofline-based FPGA Accelerator [55] Embedded FPGA Accelerator [98] DeepBurning [155] OpenCL-based FPGA Accelerator [80] Caffeine [153], [162] fpgaConvNet [165] Loop Unrolling [78], [168] Throughput-Optimized FPGA Accelerator [170] FP-DNN [171] FINN [181] Customized CONV Loop Accelerator [83] Latency-Driven Design for FPGA-based CNNs [183] DLA [188] Winograd-based CNN Accelerator [189] OpenCL-based Architecture for Accelerating CNNs [190] Multi-CLP Accelerator for CNNs [192] Automated Systolic Array Architecture for CNN [195] End-to-End Scalable FPGA Accelerator [196] DLAU [197] An Automatic RTL Compiler for High-Throughput Deep CNNs [199] Intel's DLA [200] Angel-Eye [60] Optimizing the CONV Operation to Accelerate DNNs on FPGA [204] Loop Unrolling El-Maleh's research interests are in the areas of synthesis, testing, and verification of digital systems. In addition, he has research interests in defect and soft-error tolerance design, VLSI design, design automation and efficient FPGA implementations of deep learning algorithms and data compression techniques.…”

Section: Acknowledgmentmentioning

confidence: 99%

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

2019

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Due to recent advances in digital technologies, and availability of credible data, an area of artificial intelligence, deep learning, has emerged, and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolution neural networks (CNNs) have demonstrated their effectiveness in image detection and recognition applications. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve desired performance levels. Consequently, hardware accelerators that use application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and graphic processing units (GPUs) have been employed to improve the throughput of CNNs. More precisely, FPGAs have been recently adopted for accelerating the implementation of deep learning networks due to their ability to maximize parallelism as well as due to their energy efficiency. In this paper, we review recent existing techniques for accelerating deep learning networks on FPGAs. We highlight the key features employed by the various techniques for improving the acceleration performance. In addition, we provide recommendations for enhancing the utilization of FPGAs for CNNs acceleration. The techniques investigated in this paper represent the recent trends in FPGA-based accelerators of deep learning networks. Thus, this review is expected to direct the future advances on efficient hardware accelerators and to be useful for deep learning researchers.

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“…In [15] a latency-driven design method is presented as an extension of the fpgaConvNet modeling framework [14]. This work models CNNs using the synchronous dataflow (SDF) model of computation.…”

Section: Related Workmentioning

confidence: 99%

Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications

Mousouliotis

Petrou

2019

Lecture Notes in Computer Science

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0000−0001−9621−924X] , Loukas P. Petrou [0000−0001−5760−2043] Abstract. Recently, the field of deep learning has received great attention by the scientific community and it is used to provide improved solutions to many computer vision problems. Convolutional neural networks (CNNs) have been successfully used to attack problems such as object recognition, object detection, semantic segmentation, and scene understanding. The rapid development of deep learning goes hand by hand with the adaptation of GPUs for accelerating its processes, such as network training and inference. Even though FPGA design exists long before the use of GPUs for accelerating computations and despite the fact that high-level synthesis (HLS) tools are getting more attractive, the adaptation of FPGAs for deep learning research and application development is poor due to the requirement of hardware design related expertise. This work presents a workflow for deep learning mobile application acceleration on small low-cost low-power FPGA devices using HLS tools. This workflow eases the design of an improved version of the Squeeze-Jet accelerator used for the speedup of mobile-friendly low-parameter ImageNet class CNNs, such as the SqueezeNet v1.1 and the ZynqNet. Additionally, the workflow includes the development of an HLS-driven analytical model which is used for performance estimation of the accelerator. This model can be also used to direct the design process and lead to future design improvements and optimizations.

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Latency-driven design for FPGA-based convolutional neural networks

Cited by 80 publications

References 16 publications

Cascade^CNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks

Cascade^CNN: Pushing the Performance Limits of Quantisation in Convolutional Neural Networks

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications

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