Lateral Buried Growth of N⁺-InGaAs Source/Drain Region to Undercut InGaAs Channel Structure for High Drive Current N-type MOSFET

Abstract

IntroductionAccording to ITRS [1], III-V semiconductor device technology will potentially be introduced into LSI technology for realizing circuits with greater capabilities than current CMOS circuits. In fact, logic applications using III-V devices have already been researched [2]- [4]. In previous researches, conventional InP-based transistors were fabricated as HEMT device structures [2]-[4]. However, a selective strongly doped source and drain (S/D) region is required in order to achieve high current density and low access resistance between the source and the channel with an enhancement mode [5,6]. However, ion implantation technology in InP-based materials is not yet sufficiently advanced. Thus, regrowth technology is a promising alternative technique. Furthermore, a slight overlap between the gate electrode and source is also necessary to improve the average velocity of electrons at the source end of the channel. Regrowth source regions have to penetrate under the gate electrodes. We have reported the lateral buried growth of n + -InGaAs in order to build a contact with a quantum well channel under the SiO 2 dummy gate and regrown source region.