Latin squares for parallel array access

Kim, K.; Prasanna, Viktor K.

doi:10.1109/71.219753

Cited by 53 publications

(36 citation statements)

References 21 publications

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“…Such an approach is limited by the implementable registers size and high routing complexity -in contrast to the current proposal, which allows arbitrary larger data to be accessed. Compared to [1], [3], [5]- [8], [11], [12], [14], our scheme enables higher scalability and lower number of memory modules. This directly affects the design complexity, which has been proven to be very low in our case.…”

Section: Experimental Results and Related Workmentioning

confidence: 99%

“…Neither of the functions proposed in [4] is separable, which leads to an extensive number of address generation and module assignment logic. In [5], the authors propose a scheme based on Latin squares and capable of accessing square blocks out of arrays but not from random positions. Similar drawbacks has the scheme proposed in [6].…”

Section: Experimental Results and Related Workmentioning

confidence: 99%

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Multimedia rectangularly addressable memory

Kuzmanov

Gaydadjiev

Vassiliadis

2006

IEEE Trans. Multimedia

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Abstract-We propose a scalable data alignment scheme incorporating module assignment functions and a generic addressing function for parallel access of randomly aligned rectangular blocks of data. The addressing function implicitly embeds the module assignment functions and it is separable, which potentially enables short critical paths and saves hardware resources. We also discuss the interface between the proposed memory organization and a linearly addressable memory. An implementation, suitable for MPEG-4 is presented and mapped onto an FPGA technology as a case study. Synthesis results indicate reasonably small hardware costs in the order of up to a few thousand FPGA slices for an exemplary 512 1024 two-dimensional (2-D) addressable space and a range of access pattern dimensions. Experiments suggest that speedups close to 8 can be expected when compared to linear addressing schemes.

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Section: Experimental Results and Related Workmentioning

confidence: 99%

Section: Experimental Results and Related Workmentioning

confidence: 99%

Multimedia rectangularly addressable memory

Kuzmanov

Gaydadjiev

Vassiliadis

2006

IEEE Trans. Multimedia

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“…Some declustering techniques utilize information about query distribution [22], [23]. The use of combinatorial designs including Latin squares [28] and Latin cubes [15] is proposed for a variant of the declustering problem where array blocks are distributed among multiple memory modules. When the number of disks is a power of two, a declustering scheme that achieves the lower bound is proposed in [3].…”

Section: Introductionmentioning

confidence: 99%

Analysis and Comparison of Replicated Declustering Schemes

Tosun

2007

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Declustering distributes data among parallel disks to reduce the retrieval cost using I/O parallelism. Many schemes were proposed for the single-copy declustering of spatial data. Recently, declustering using replication gained a lot of interest and several schemes with different properties were proposed. An in-depth comparison of major schemes is necessary to understand replicated declustering better. In this paper, we analyze the proposed schemes, tune some of the parameters, and compare them for different query types and under different loads. We propose a three-step retrieval algorithm for the compared schemes. For arbitrary queries, the dependent and partitioned allocation schemes perform poorly; others perform close to each other. For range queries, they perform similarly with the exception of smaller queries in which random duplicate allocation (RDA) performs poorly and dependent allocation performs well. For connected queries, partitioned allocation performs poorly and dependent allocation performs well under a light load.

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“…In many cases, the operands for parallel processing can be stored so that conflict-free access to certain patterns is possible, e.g., rows, columns, blocks, forward-and backward-diagonals [13,14]. These are called the access formats.…”

Section: Parallel Memorymentioning

confidence: 99%

Parallel Memory Architecture for TTA Processor

Tanskanen

Pitkänen

Makinen³

et al.

Lecture Notes in Computer Science

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Abstract.A conflict resolving parallel data memory system for Transport Triggered Architecture (TTA) is described. The architecture is generic and reusable to support various application specific designs. With parallel memory, more area and power consuming multi-port memory can be replaced with single-port memory modules. Number of ports can be increased over what is available on a design library for multi-port memories. In an FFT TTA example, dual-port data memory was replaced by the proposed architecture. To avoid memory conflicts, the original code was rescheduled and the TTA core was regenerated for the new schedule. The original memory required an area higher by a factor of 3.38 and energy higher by a factor of 1.70. In this case, the energy consumption of the processor core increased so that system energy consumption remained about the same. However, the original system required an area higher by a factor of 1.89.

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Latin squares for parallel array access

Cited by 53 publications

References 21 publications

Multimedia rectangularly addressable memory

Multimedia rectangularly addressable memory

Analysis and Comparison of Replicated Declustering Schemes

Parallel Memory Architecture for TTA Processor

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