Lattice-Traversing Design Space Exploration for High Level Synthesis

Ferretti, Lorenzo; Ansaloni, Giovanni; Pozzi, Laura

doi:10.1109/iccd.2018.00040

Cited by 37 publications

(18 citation statements)

References 22 publications

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“…Instead of learning a predictive model, they invoke the HLS tool every time to evaluate the quality of the design. To guide the search, they either exploit general applicationoblivious heuristics (e.g., simulated annealing [33] and genetic algorithm [41]) or they develop their own heuristics [22,23,42]. S2FA [57] employ multi-armed bandit [24] to combine a set of heuristic algorithms including uniform greedy mutation, differential evolution genetic algorithm, particle swarm optimization, and simulated annealing.…”

Section: Model-free Approachesmentioning

confidence: 99%

“…However, as we will present in Section 5.1, general hyper-heuristic approaches are unreliable for finding the high quality of result (QoR) design configuration. Moreover, the authors in [22,23] claim that Pareto-optimal design points cluster together. They exploit an initial sampling to build the first approximation of the Pareto frontier and require local searches to explore other candidates.…”

Section: Model-free Approachesmentioning

confidence: 99%

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AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Sohrabizadeh

Gao³

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

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Adopting FPGA as an accelerator in datacenters is becoming mainstream for customized computing, but the fact that FPGAs are hard to program creates a steep learning curve for software programmers. Even with the help of high-level synthesis (HLS) , accelerator designers still have to manually perform code reconstruction and cumbersome parameter tuning to achieve optimal performance. While many learning models have been leveraged by existing work to automate the design of efficient accelerators, the unpredictability of modern HLS tools becomes a major obstacle for them to maintain high accuracy. To address this problem, we propose an automated DSE framework— AutoDSE —that leverages a bottleneck-guided coordinate optimizer to systematically find a better design point. AutoDSE detects the bottleneck of the design in each step and focuses on high-impact parameters to overcome it. The experimental results show that AutoDSE is able to identify the design point that achieves, on the geometric mean, 19.9× speedup over one CPU core for MachSuite and Rodinia benchmarks. Compared to the manually optimized HLS vision kernels in Xilinx Vitis libraries, AutoDSE can reduce their optimization pragmas by 26.38× while achieving similar performance. With less than one optimization pragma per design on average, we are making progress towards democratizing customizable computing by enabling software programmers to design efficient FPGA accelerators.

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Section: Model-free Approachesmentioning

confidence: 99%

Section: Model-free Approachesmentioning

confidence: 99%

AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Sohrabizadeh

Gao³

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

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show abstract

“…None of these approaches model directive placement and configuration for multiple HLS code targets and comprehensive FPGA design spaces. Researchers have also constructed lattices for HLS design space exploration [16]. Lattices are promising but thus far have considered only two objectives, latency and area, rather than the multiple objectives required for FPGA implementation.…”

Section: Related Workmentioning

confidence: 99%

Bayesian Optimization for Efficient Accelerator Synthesis

Mehrabi

Manocha

Lee

et al. 2020

ACM Trans. Archit. Code Optim.

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Accelerator design is expensive due to the effort required to understand an algorithm and optimize the design. Architects have embraced two technologies to reduce costs. High-level synthesis automatically generates hardware from code. Reconfigurable fabrics instantiate accelerators while avoiding fabrication costs for custom circuits. We further reduce design effort with statistical learning. We build an automated framework, called Prospector, that uses Bayesian techniques to optimize synthesis directives, reducing execution latency and resource usage in field-programmable gate arrays. We show in a certain amount of time that designs discovered by Prospector are closer to Pareto-efficient designs compared to prior approaches. Prospector permits new studies for heterogeneous accelerators.

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“…An analytic design exploration approach for FPGA-HLS is introduced in [160] which represents the design space as a lattice [161]. It provides a guided directive (pragma) selection and directive value-assignment methodology for very large design spaces by locally searching in the n-dimensional lat-This work is licensed under a Creative Commons Attribution 4.0 License.…”

Section: ) Loop Pipeliningmentioning

confidence: 99%

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

et al. 2020

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Heterogeneous computing systems with tightly coupled processors and reconfigurable logic blocks provide great scope to improve software performance by executing each section of code on the processor or custom hardware accelerator that best matches its requirements and the system optimisation goals. This paper is motivated by the idea of a software tool that can automatically accomplish the task of deploying code, originally written for a conventional computer, to the processors and reconfigurable logic blocks in a heterogeneous system. We undertake an extensive survey of high-level synthesis tools to determine how close we are to this vision, and to identify any capability gaps. The survey is structured according to a new framework that clearly expresses the relationships between the many tools surveyed. We find that none of the existing tools can deploy general high-level code without manual intervention. Logic synthesis from arbitrary high-level code remains an open problem with dynamic data structures, function pointers and recursion all presenting challenges. Other challenges include automating the tasks of code partitioning, optimisation and design space exploration.

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Lattice-Traversing Design Space Exploration for High Level Synthesis

Cited by 37 publications

References 22 publications

AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators

Bayesian Optimization for Efficient Accelerator Synthesis

Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains

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