Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

Hung, Chun-Hsiung; Chang, Meng‐Fan; Yang, Yawei; Kuo, Yao-Jen; Lai, Tzu-Neng; Shen, Shin-Jang; Hsu, Jo-Yu; Hung, Shuo-Nan; Lue, Hang-Ting; Shih, Yung‐Feng; Huang, Shih-Lin; Chen, Ti-Wen; Chen, Tzung Shen; Chen, Chung Kuang; Hung, Chi-Yu; Lu, Chih‐Yuan

doi:10.1109/jssc.2015.2413841

Cited by 30 publications

(13 citation statements)

References 18 publications

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“…Among the three axes, we expect the variation along the z-axis (i.e., layer-to-layer variation) to be the most significant, due to the new challenge of stacking multiple flash cells across layers. Prior work has shown that current circuit etching technologies are unable to produce identical 3D NAND cells when punching through multiple stacked layers, leading to significant variation in the error characteristics of flash cells that reside in different layers [38,92].…”

Section: Layer-to-layer Process Variationmentioning

confidence: 99%

“…Prior work proposes circuit-level and systemlevel techniques to tolerate layer-to-layer process variation in 3D NAND flash memory. Two recent works propose to use different read reference voltages for different layers [38,96], which is similar to the LaVAR technique that we propose in Section 6.1. Unlike our work, these prior works do not (1) design a detailed mechanism like LaVAR to learn and use the V opt in a lookup table, or (2) evaluate their techniques using real characterization data.…”

Section: Related Workmentioning

confidence: 99%

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Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

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Compared to planar (i.e., two-dimensional) NAND flash memory, 3D NAND flash memory uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip. This allows 3D NAND flash memory to increase storage density using a much less aggressive manufacturing process technology than planar NAND flash memory. The circuit-level and structural changes in 3D NAND flash memory significantly alter how different error sources affect the reliability of the memory.In this paper, through experimental characterization of real, state-of-the-art 3D NAND flash memory chips, we find that 3D NAND flash memory exhibits three new error sources that were not previously observed in planar NAND flash memory: (1) layer-to-layer process variation, a new phenomenon specific to the 3D nature of the device, where the average error rate of each 3D-stacked layer in a chip is significantly different; (2) early retention loss, a new phenomenon where the number of errors due to charge leakage increases quickly within several hours after programming; and (3) retention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the data value stored in the neighboring cell.Based on our experimental results, we develop new analytical models of layer-to-layer process variation and retention loss in 3D NAND flash memory. Motivated by our new findings and models, we develop four new techniques to mitigate process variation and early retention loss in 3D NAND flash memory. Our first technique, Layer Variation Aware Reading (LaVAR), reduces the effect of layer-to-layer process variation by fine-tuning the read reference voltage separately for each layer. Our second technique, Layer-Interleaved Redundant Array of Independent Disks (LI-RAID), uses information about layer-to-layer process variation to intelligently group pages under the RAID error recovery technique in a manner that reduces the likelihood that the recovery of a group fails significantly earlier than the recovery of other groups. Our third technique, Retention Model Aware Reading (ReMAR), reduces retention errors in 3D NAND flash memory by tracking the retention time of the data using our new retention model and adapting the read reference voltage to data age. Our fourth technique, Retention Interference Aware Neighbor-Cell Assisted Correction (ReNAC), adapts the read reference voltage to the amount of retention interference a page has experienced, in order to re-read the data after a read operation fails. These four techniques are complementary, and can be combined together to significantly improve flash memory reliability. Compared to a state-of-the-art baseline, our techniques, when combined, improve flash memory lifetime by 1.85×. Alternatively, if a NAND flash vendor wants to keep the lifetime of the 3D NAND flash memory device constant, our techniques reduce the storage overhead required to hold error correction information by 78.9%.

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Section: Layer-to-layer Process Variationmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Luo

Ghose

Cai

et al. 2018

Proc. ACM Meas. Anal. Comput. Syst.

View full text Add to dashboard Cite

show abstract

“…A split-gate architecture was also proposed in order to relax the lithography on the select gates (split-gate architecture). Several other innovations have led to a very compact layout of the VG NAND and its operation [29][30][31][32].…”

Section: Single-gate Vertical Channel (Sgvc) Architecturementioning

confidence: 99%

“…It must be noted here that the overall performance of the 3D NAND architectures should be finally evaluated after a proper system implementation. In fact, several drawbacks of an architecture can be corrected or mitigated by implementing ad hoc program algorithms and ECC [4,17,31,32,[34][35][36][37].…”

Section: Comparison Between Ct Flat Cell and Gaa Cell Structuresmentioning

confidence: 99%

3D NAND Flash Based on Planar Cells

Silvagni¹

2017

Computers

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Abstract:In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a "punch-and-plug" process-with gate-all-around (GAA) cell devices-against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production.

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“…The layers with the higher operating point will result in higher background pattern dependency. In order to level this kind of dependency, a method was proposed where each bitline is pre-charged to specific layer-dependent voltage instead of discharging all the bitlines to GND during the setup phase [31].…”

Section: Read Operationmentioning

confidence: 99%

3D VG-Type NAND Flash Memories

Silvagni

2016

3D Flash Memories

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Solid State Disk applications have been the main drivers for the cost reduction of NAND Flash memory. Technology scaling limits have been almost reached and new directions were investigated for a decade. 3D NAND appeared as the most promising and short term viable solution to the scaling problem. 3D NAND offers the possibility to keep scaling memory density beyond 2D NAND 1z nm technology and opens new landscapes if the technology hurdles can be definitely overcome. Additionally Multi bit per cell technology is applicable to 3D NAND as well; therefore, the storage capacity growth trend is not going to meet the inflection point soon. Big Data storage demand remains certainly the driver for the rapidity of 3D NAND to become industry mainstream.With respect to the flat 2D NAND Flash, three-dimensional architectures demand a more challenging approach to deal with process, design architectures, parasitic effects, testing. At the time of writing this chapter, 3D technology is moving into production inside solid state storage solutions; however, those NAND chips aren't commercially available as raw components. 3D NAND chips are used by vertically integrated manufacturers and few partners to build the storage systems under a strict control on the usage. Technology solutions are still diversified among the few players in the 3D arena and no unique mainstream solution is emerged yet.In this chapter the principal architectural pieces of 3D NAND will be reviewed putting the focus on one of them: VG-Type, Vertical Gate 3D NAND.

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Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations

Cited by 30 publications

References 18 publications

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation

3D NAND Flash Based on Planar Cells

3D VG-Type NAND Flash Memories

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