Layer‐Controlled Low‐Power Tunneling Transistors Based on SnS Homojunction

Abstract

Utilizing the layer‐controlled bandgap of a 2D material is an effective way of improving a tunneling field‐effect transistor (TFET) device's performance because of the narrowing tunneling barrier. An ab initio quantum transport method is used to study the SnS homojunction TFETs at a sub‐10 nm scale through layer controlling. The optimal SnS homojunction TFET has a bilayer SnS as the source electrode, which possesses a low leakage current like the ML SnS TFET and a high on‐state current like the BL SnS TFET. The low SSave_4dec (subthreshold swing over four decades of the drain currents) of ≈47–48 mV dec−1 and I60 (drain current at 60 mV dec−1) of ≈1.1–1.2 µA µm−1 implies the BL source SnS TFET, a fast low‐power (LP) device. The optimal BL source SnS TFET with a gate length of Lg = 10 nm exceeds the LP device requirement of the International Technology Roadmap for Semiconductors (ITRS) (2013 version), and its negative capacitance counterparts can exceed the ITRS 2028 target for LP device at Lg = 5 nm.

2D materials-based nanoscale tunneling field effect transistors: current developments and future prospects

“…The MX materials are also found to be effective for hetero-tunneling junction design by varying layer thickness at different regions of nanoscale TFET. In this line, using a bilayer SnS in source/drain regions with monolayer SnS in the channel region, a SS below 50 mV/dec over four orders of current has been demonstrated 108 .…”

Electrochemical ammonia synthesis: fundamental practices and recent developments in transition metal boride, carbide and nitride-class of catalysts

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Comprehensive understanding of intrinsic mobility and sub-10 nm quantum transportation in Ga2SSe monolayer

“…The introduction of an optimized UL structure can enhance the device performance by increasing the effective channel length and reducing the probability of electron tunneling, which not only suppresses the tunneling current between the source and the drain electrodes in a short channel but also reduces the coupling between the source and the drain and the channel. 63,64 However, the control abilities of the top and bottom gates are limited since the gates do not cover the UL area; if the UL structure is too long, it will adversely reduce the performance of the FET device. Therefore, to achieve the optimized UL length for the Ga 2 SSe FET device, the transfer characteristic curves and the corresponding I on data with different UL lengths are represented in Fig.…”