Layered Approach to Intrinsic Evolvable Hardware using Direct Bitstream Manipulation of Virtex II Pro Devices

Abstract

An integrated platform for fast genetic operators is presented to support intrinsic evolution on Xilinx Virtex II Pro Field Programmable Gate Arrays (FPGAs). Dynamic bitstream compilation is achieved by directly manipulating the bitstream using a layered design. Experimental results on a case study have shown that a full design as well as a full repair is achievable using this platform with an average time of 0.4 microseconds to perform the genetic mutation, 0.7 microseconds to perform the genetic crossover, and 5.6 milliseconds for one input pattern intrinsic evaluation. This represents a performance advantage of three orders of magnitude over JBITS and more than seven orders of magnitude over the Xilinx design tool driven flow for realizing intrinsic genetic operators on a Virtex II Pro device.

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

“…These GA settings are based on similar previous works [2], [27] and validated through experiment. This parameter set produced the best tradeoff in GA performance and memory requirements to store the individuals of the population.…”

“…Typical performance plots in terms of fitness with respect to time for both NDER and CER are illustrated in Figure 10. This overall behavior of conventional GA may be attributed to the I/O characteristics and the sizes of the chosen circuits, as compared to the ones used in previous works [12], [14], [23], [27], [39], [40]. For instance, it is shown in [40] that the recovery time increases with increasing number of output lines.…”

“…There has also been work to reduce the overall evolution run time by operating directly on the bitstream used to configure the reconfigurable device, e.g. [27] demonstrate self-recovery of a 4-bit x 4-bit adder on a Xilinx Virtex II Pro FPGA device in as low as 0.4 µseconds.…”

A bird's eye view of FPGA-based Evolvable Hardware

“…These issues are more prominent as the critical portions of bitstream representation are proprietary. Recently Oreifej et al [34] proposed an approach to carry out bitstream manipulation for Xilinx Virtex-II Pro device. They have developed data structures and an Application Programming Interface (API) to perform mapping operations directly on the bitstream to modify Lookup Table (LUT) configurations and reconfigure the device.…”

“…An interesting preliminary work is the one described in [34]. It would be very interesting to apply such systems in the field of automatic control and fault tolerance.…”