Layout decomposition for quadruple patterning lithography and beyond

Yu, Bei; Pan, David Z.

doi:10.1109/dac.2014.6881380

Cited by 13 publications

(6 citation statements)

References 24 publications

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“…The basic idea is to formulate a vector programming problem by introducing a set of unit vectors. For example, in quadruple patterning, four vectors are introduced in the SDP formulation from [5]: (0, 0, 1), (0, 2…”

Section: Lele-type Mplmentioning

confidence: 99%

“…The generalized SDP formulation for k-patterning layout decomposition where k ≥ 4 is shown as follows [5],…”

Section: Figure 3: Vector Based Color Representationsmentioning

confidence: 99%

“…Both LELE-based and spacer-based double/multiple patterning technologies have been used in fabricating critical layers which have very dense layouts, e.g., SADP has been widely used to fabricate FinFETs while LELE-based double/triple patterning has been used to print M1 layers [2][3][4]. In the future, MPL will still be a viable lithography solution for sub-10nm technology node, either continuing pushing 193nm lithography, e.g., using quadruple patterning [5], or used along with other lithography techniques, such as extreme ultraviolet lithography (EUVL), electric beam lithography (EBL), and directed self-assembly (DSA) [6].…”

Section: Introductionmentioning

confidence: 98%

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Pushing multiple patterning in sub-10nm

Pan

Liebmann

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor industry has been pushing the 193nm immersion lithopgrahy using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been extensively studied, first on double patterning, then on triple or even quadruple patterning. Meanwhile, many studies have shown that it is very important to consider MPL implications at early physical design stages so that the overall design and manufacturing closure can be reached. In this paper, we provide a comprehensive overview on the state-of-the-art research results for MPL, from synergistic mask synthesis to physical design. We will also discuss the open problems as to pushing multiple patterning in sub-10nm.

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Section: Lele-type Mplmentioning

confidence: 99%

“…The generalized SDP formulation for k-patterning layout decomposition where k ≥ 4 is shown as follows [5],…”

Section: Figure 3: Vector Based Color Representationsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

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Pushing multiple patterning in sub-10nm

Pan

Liebmann

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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“…The first ILP formulation for TPL comes from Yu et al [63] and a semidefinite programming (SDP) based algorithm is proposed to achieve approximate results. The SDP formulation is further extended to handle arbitrary k-coloring problem [64], shown as (1). Here k equals to 3 for TPL and 4 for QPL.…”

Section: Mpl Layout Decompositionmentioning

confidence: 99%

Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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“…The layout decomposition problem has been well studied. 4,[9][10][11][12][13][14][15] In addition, the related constraints have been considered in early physical design stages, like routing, 16,17 standard cell design, 18,19 and detailed placement. 19 However, only few attempts have been made to address the LELE-EC layout decomposition problem.…”

Section: Illustrates Anmentioning

confidence: 99%

Triple patterning lithography (TPL) layout decomposition using end-cutting

Yu¹,

Gao²,

Pan³

2013

SPIE Proceedings

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Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and endcut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the conflict number and the stitch number.

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Layout decomposition for quadruple patterning lithography and beyond

Cited by 13 publications

References 24 publications

Pushing multiple patterning in sub-10nm

Pushing multiple patterning in sub-10nm

Design for manufacturability and reliability in extreme-scaling VLSI

Triple patterning lithography (TPL) layout decomposition using end-cutting

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