Layout-dependent proximity effects in deep nanoscale CMOS

Faricelli, J.

doi:10.1109/cicc.2010.5617407

Cited by 57 publications

(22 citation statements)

References 25 publications

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“…In order to drive all subtractors/comparators, frontend S/Hs typically use an amplifier or a source follower, which may introduce distortion and consume a significant amount of power. This can be avoided by employing passive switched capacitor circuits 7 before the comparators, which sample the input and subtract if from the references [32,53]. This distributed S/H solution is also illustrated in Fig.…”

Section: Multi-step Subranging Adc Architecturesmentioning

confidence: 98%

“…18 Also, device matching is becoming more dependent on its surroundings [7,76]. As transistors further scale, the quantum effects will eventually dominate and degrade matching considerably [6].…”

Section: Consequences Of Technology Scaling On Analog Circuitsmentioning

confidence: 99%

“…The DAC non-linearity is modeled with an output dependent gain factor, 6 similarly to what was done in Fig. 6c vDAC [2] vDAC [3] vDAC [4] vDAC [5] vDAC [6] vDAC [7] vDAC [2] vDAC [3] vDAC [4] vDAC [5] vDAC [6] vDAC [7] However, since each output code is now determined by different subtractors/ comparators, their offsets generate different deviations on the ADC code transition levels, causing distortion (and not a harmless shift on the overall transfer function, as in the SAR ADC). So, to ensure the deviations on the code transition levels of the ADC are below 1 LSB, the offsets of the subtractors/comparators must all be lower than that value [32].…”

Section: Single and Multi-bit Adc Architecturesmentioning

confidence: 99%

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Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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This chapter discusses the architectures of Nyquist rate Analog-toDigital Converters (ADCs), that are embedded in systems-on-chip (SoCs) implementing some of the most widespread mobile communication, wireless and wireline connectivity standards. The typical requirements for these ADCs are presented, and the main conversion architectures are described in terms of the fundamental operations realized inside them. This constitutes a unified treatment that relates all architectures, thus providing a deeper understanding of their fundamental limitations and trade-offs. We then discuss some of the solutions recently published in the literature to improve ADC energy efficiency. Finally we disclose implementation details from two 12 bit digitally calibrated, high-speed ADCs, using the pipeline and SAR architectures.

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Section: Multi-step Subranging Adc Architecturesmentioning

confidence: 98%

Section: Consequences Of Technology Scaling On Analog Circuitsmentioning

confidence: 99%

Section: Single and Multi-bit Adc Architecturesmentioning

confidence: 99%

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Recent Advances and Trends in High-Performance Embedded Data Converters

Figueiredo¹

2014

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing

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“…Scaling has been accompanied by various techniques to boost the device's performance [3]- [5]. Among them, strain engineering [6], [7] stands significant from other techniques, by providing a large enhancement of the carriers mobility [8]. If the nanoscale integrated circuits (ICs) are additionally intended to be manufactured on ultra-thin Si-chips for bendable electronics [9], then external global stress get introduced during or due to bending and twisting of the chip.…”

Section: Introductionmentioning

confidence: 99%

“…1 SPICE simulations can predict the response of devices produced via various standard technologies. The local-induced stress-effects [6], [12] have been intensively studied and included in device compact models [13], [14]. On the other hand, the effects of external-induced stress are an ongoing investigation and the exist compact models are inadequate for electronics over flexible and bendable substrates [15].…”

Section: Introductionmentioning

confidence: 99%

Device modelling of bendable MOS transistors

Heidari

Navaraj

Toldi

et al. 2016

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-This paper presents the directions for computer aided design, modelling and simulation of bendable MOSFET transistors towards futuristic bendable ICs. In order to compensate the bending stress a generalised geometry variation is discussed. Based on drain-current and threshold-voltage parameters varying under the bending stress, a Verilog-A compact model is proposed and describes I-V characteristics of a MOSFET in a standard 0.18-µm CMOS technology. This model has been compiled into Cadence environment to predict value and orientation of the bending stress. The proposed model validates against macro-model simulation results, and agrees for both the electron and hole conduction. It has been found that there is significant performance advantage in process-induced uniaxial stressed n-MOSFET, exhibiting a smaller drain-current variation and threshold voltage shift by monitoring the bending stress and changing the supply voltage.

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