Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint

Abstract

We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D)

Test planning and test access mechanism design for stacked chips using ILP

“…Test planning to reduce test cost given by test time and DfT hardware has for SICs been addressed in [10,11]. The schemes do however not assume any particular DfT architecture and make it difficult to reuse DfT hardware added for wafer sort test at package testing.…”

A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper

“…Subsequent papers on 3D-SIC testing implicitly propose a test access architecture, while focusing on optimizing the design parameters of that architecture to minimize the resulting test length and/or the associated wire length [13,14,40,41]. Wu et al [40] propose three scan chain optimization algorithms, taking the length of TSV-based interconnects into account.…”

“…The paper lacks realistic constraints on wafer and packaged stack test access, due to which it unrealistically allows TAMs to start and end at any stack tier. Successor paper [14] remedies this partly, by working with pre-bond tests that are applied through dedicated probe pads at the die in question, for which a maximum count is assumed. The paper proposes heuristics that determine a post-bond stack test architecture, from which segments are reused as much as possible to build additional die-level test architectures for the pre-bond tests, while meeting the maximum probe pad count constraint and minimizing test length and TAM wire length.…”

“…As long as that is the case, it is a requirement to provide dedicated probe pads for pre-bond wafer test access [14,17,23] for all dies in the stack, apart from the bottom die.…”

Time-multiplexed test access architecture for stacked integrated circuits

“…The configurable options of each lane of the flexible parallel test bus include direction (In, Out or BiDir) and edge of clock for sending output (positive or negative). Generally, besides a sequential test access to each die, the test access optimization schemes can result in daisy-chained and/or parallel accesses [5,6,7]. Even though there is a separate TAP controller on each die of P1838 complied stack, all wrapped dies stay in a common state, e.g., shift, capture, update, because control signals are broadcast to them.…”