Layout verification and optimization based on flexible design rules

Yang, Jie; Capodieci, Luigi; Sylvester, Dennis

doi:10.1117/12.658982

Cited by 9 publications

(6 citation statements)

References 5 publications

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“…Based on this, new space rules should be set up specifying larger tip-to-tip space or larger space to the right and left. In fact, these additional space rules have been set for many more unique cases of line end close to the octagonal line in a "dense environment" that cannot allow an accurate OPC [50]. Additional metal space rules are related to the voltage difference between the two metal lines of two different nets (Mx.S.4).…”

Section: Metal Width and Space Rulesmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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The continuous scaling needed for better performance and higher density has introduced some new challenges to the back end of line (BEOL) in terms of layout and design. Reductions in metal line width, spacing, and thickness require major changes in both process and design environments. Advanced deep-submicron layout design rules (DRs) should now consider many new proximity effects and reliability concerns due to high electrical fields and currents, planarization-related coverage effects, etc. It is, therefore, necessary to redefine many of the common DRs. For example, space rules now have a complex definition, including both line width and parallel length. In addition, new rules have been introduced to represent the challenges of reliability such as stress-induced voids, time-dependent dielectric breakdowns of intermetal dielectrics, dependency on misalignment, sensitivity to double patterning, etc. This review describes a set of copper (Cu) BEOL layout design rules, as used in technologies featuring lengths ranging from 0.15 µm to 20 nm. The verification of layout rules and sensitivity issues related to them are presented. Reliability-related aspects of some rules, like space, width, and via density, are also discussed with additional design-for-manufacturing layout recommendations.Keywords: back end of line; layout design rules; copper technology; inter-metal dielectric time-dependent dielectric breakdown (IMD-TDDB) M2-M5) have similar or slightly increased thicknesses when compared with the M1 layer, and are mostly used for connections between various devices. Semi-global (M6-M7, 0.35-0.9 µm) and global (M8, 0.9-3.3 µm) lines are used for power buses, transmission lines, and inductors.In order to achieve a tight pitch of M1 and semi-global lines with a high-density design, interconnects are used to connect high-density-logic transistors, standard cells, and other functional blocks in a system on chip (SoC). In general, application-specific integrated circuits (ASICs) and SoCs tend to use a combination of interconnect metals with a large number of MI lines (semi-global) for applications such as highly parallel graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and multi-core smartphone processors (multiple central processing unit (CPU) and GPU cores). In contrast, devices for applications of radio frequency CMOS (RFCMOS), millimeter wave (mmWave), and WiFi use several layers of semi-global and global lines for inductors, transmission lines, and more. From a practical point of view, the set of rules relating to specific types of interconnect do not change based on their use in various applications. This is because many electronic design automation (EDA) tools such as design rule checks (DRCs), BEOL RC modeling, and even dummy fill insertions also need to be adjusted. Instead, the platform process design kit (PDK) includes a large set of metal combinations so that the designer may select one based on their integrated circuit (IC) needs. For example, WiFi ICs, designed using the 65 nm RFCMOS...

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Section: Metal Width and Space Rulesmentioning

confidence: 99%

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Shauly

2018

JLPEA

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“…Consequently, scoring function is generated as we find value of weighting coefficients to minimize cost. (2) where m is the number of hot-spot.…”

Section: Hot-spotsmentioning

confidence: 99%

Score-based fixing guidance generation with accurate hot-spot detection method

Park

Kim

Choi³

et al. 2009

SPIE Proceedings

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SWhile predicting and removing of lithographic hot-spots are a matured practice in recent semiconductor industry, it is one of the most difficult challenges to achieve high quality detection coverage and to provide designer-friendly fixing guidance for effective physical design implementation. In this paper, we present an accurate hot-spot detection method through leveling and scoring algorithm using weighted combination of image quality parameters, i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF) which can be obtained through lithography simulation. Hot-spot scoring function and severity level are calibrated with process window qualification results. Least-square regression method is used to calibrate weighting coefficients for each image quality parameter. Once scoring function is obtained with wafer results, it can be applied to various designs with the same process. Using this calibrated scoring function, we generate fixing guidance and rule for the detected hot-spot area by locating edge bias value which can lead to a hot-spot free score level. Fixing guidance is generated by considering dissections information of OPC recipe. Finally, we integrated hot-spot fixing guidance display into layout editor for the effective design implementation. Applying hot-spot scoring and fixing method to memory devices of the 50nm node and below, we could achieve a sufficient process window margin for high yield mass production.

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“…The lithography simulation tool is also used for applications such as model-based design rule checks [3][4][5][6][7] and process window analysis, [8][9][10] as well as timing analysis based on simulated critical dimensions. 11 Other than these applications, there could be different applications of the lithography simulation tool such as design for manufacturability ͑DFM͒ rule development and transistor effective parameter back-annotation, as developed and described in this work.…”

Section: Introductionmentioning

confidence: 99%

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

Wang

et al. 2007

J. Micro/Nanolith. MEMS MOEMS

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We describe design house approaches for design rule developments with emphasis of valuations of pre-optical proximity correction ͑pre-OPC͒ layouts and their simulation results. To begin, we describe the procedure of the simulation model calibration. An evaluation of metrics for analyzing the design layouts is then described. Due to the unavailability of post-OPC layouts, both pre-OPC and trial-OPC simulations are studied. A range of layout pattern density, within which the pre-OPC metric follows the post-OPC's, is estimated. Within this pattern density range, pre-OPC layout then can be evaluated to identify potential process "hot spots." With this approach, a set of design for manufacturability ͑DFM͒ compliance design rules is derived and applied to the product developments for both 90-and 65-nm process technology nodes. Several hot spots in the products ͑designed with 90-nm design rules͒ are located and fixed using layout optimization guided by the DFM rules. Simulated image contours and in-line scanning electron microscope ͑SEM͒ images validate the approach. © 2007 Society of Photo-Optical Instrumentation Engineers.

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Layout verification and optimization based on flexible design rules

Cited by 9 publications

References 5 publications

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Physical, Electrical, and Reliability Considerations for Copper BEOL Layout Design Rules

Score-based fixing guidance generation with accurate hot-spot detection method

Lithography-simulation-based design for manufacturability rule development: an integrated circuit design house’s approach

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