1993
DOI: 10.1145/151646.151651
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Lazy caching

Abstract: This paper examines cache consistency conditions for multiprocessor shared memory systems. It states and motivates a weaker condition than is normally implemented. An algorithm is presented that exploits the weaker condition to achieve greater concurrency. The algorithm is shown to satisfy the weak consistency condition. Other properties of the algorithm and possible extensions are discussed.

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Cited by 92 publications
(94 citation statements)
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“…For simplicity, in both cases we consider, as in [3,5,8,18,24,26,25], that each MCSprocess has a copy (replica) of the whole shared memory. In an MCS with invalidation, some of the copies of a variable x can be "invalid" or outdated.…”
Section: Systemmentioning
confidence: 99%
See 1 more Smart Citation
“…For simplicity, in both cases we consider, as in [3,5,8,18,24,26,25], that each MCSprocess has a copy (replica) of the whole shared memory. In an MCS with invalidation, some of the copies of a variable x can be "invalid" or outdated.…”
Section: Systemmentioning
confidence: 99%
“…This value is returned to an application process that issues a read operation. New written values are propagated among MCS-processes to maintain the copies up to date [3,5,8,18]. …”
Section: Systemmentioning
confidence: 99%
“…Consequently, previous theorem-proving approaches have not been able to verify a problem of the scale of a full multiprocessor cache coherence protocol. The most significant result before our work is a manual proof of "lazy caching," a simple and abstract cache coherence algorithm [2], [13], [21]. It should be noted that using a theorem-prover typically increases the labor required to complete a proof compared with manual proof-however, the results are much more likely to be correct.…”
Section: Basic Ideamentioning
confidence: 99%
“…There are two interpretations for what it means for a distributed memory to be sequentially consistent [23], [7], [2]. The first is that every terminating multiprocessor program must produce one of the possible "results" (contents of memory and registers) that could be produced by a multiprocessor with a single shared atomic memory.…”
Section: Delayed Mode Conforms To Sequential Consistency Memory Modelmentioning
confidence: 99%
“…RELATED WORK Several protocols providing a sequentially consistent shared memory abstraction on top of an asynchronous message passing distributed system have been proposed. The protocol described in [2] implements a sequentially consistent shared memory abstraction on top of a physically shared memory and local caches. It uses an atomic n-queue update primitive.…”
Section: Introductionmentioning
confidence: 99%