LC‐GRFA: global register file assignment with local consciousness for VLIW DSP processors with non‐uniform register files

Abstract

SUMMARYEmbedded processors developed within the past few years have employed novel hardware designs to reduce the ever-growing complexity, power dissipation, and die area. Although using a distributed register file architecture is considered to have less read/write ports than using traditional unified register file structures, it presents challenges in compilation techniques to generate efficient codes for such architectures. This paper presents a novel scheme for register allocation that includes global and local components on a VLIW DSP processor with distributed register files whose port access is highly restricted. In the scheme, an optimization phase performed prior to conventional global/local register allocation, named global/local register file assignment (RFA), is used to minimize various register file communication costs. A heuristic algorithm is proposed for global RFA to make suitable decisions based on local RFA. Experiments were performed by incorporating our schemes on a novel VLIW DSP processor with non-uniform register files. The results indicate that the compilation based on our proposed approach delivers significant performance improvements, compared with the solution without using our proposed global register allocation scheme.

Achieving spilling-friendly register file assignment for highly distributed register files

“…Because the PAC DSP has a clustered organization with distributed register files, the data movement between register files in the PAC DSP is classified into intra-and intercluster communications, which means that the common cluster-assignment problem for VLIW processors [24][25][26] cannot be applied directly to the architecture. Also, the complicated communication makes it desirable to use register file assignment in handling communications, including localconscious global register file assignment [11,12], ping-pong-aware local favorable local register file assignment [6,7], and simulated-annealing local register file assignment [13]. In addition to register file assignment, the copy propagation in the original Open64 compiler has also been improved [29].…”

“…In register file assignment, we have proposed local-conscious global register file assignment [11,12], ping-pong-aware local favorable local register file assignment [6,7], and simulated-annealing local register file assignment [13] to handle the issues.…”

“…Minimizing the communication cost in the PAC DSP makes it desirable to use register file assignment to handle communications [6,7,11,12]. With the assistance of this heuristic approach, we then apply register allocation to each register file.…”

“…The PAC DSP is currently being developed at ITRI STC (Soc Technology Center of Industrial Technology Research Institute in Taiwan), and our laboratory is collaborating with ITRI STC under MOEA (Ministry of Economic Affairs) projects for the challenging work of developing high-performance and low-power tool kits for embedded systems under PAC platforms [6][7][8][9][10][11][12][13].…”

Parallel Architecture Core (PAC)—the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools

“…The ORC frontend helps to generate the intermediate representation, WHIRL, with five representation levels from "very high" to "very low", where various targetindependent optimizations are performed, such as control flow optimization, extended basic block (peephole) optimization, integrated global/local scheduling, and loop transformation at the "very low" level. We have developed specific optimization techniques in the backend for PACDSP, including copy propagation for irregular register files [17], optimal local register file assignment based on simulation annealing (SA-LRFA) [18], ping-pong aware & local favorable register file assignment (PALF-LRFA) [19], and local-conscious & global register file assignment (LC-GRFA) [20], etc. LC-GRFA is the most important optimization, which minimizes data communication costs between various registers.…”