LDO Linear Regulator with Super-source Follower

Chang, Yi-Tsung; Hung, Fu Lian; Xue, Ren Hao; Shiau, Yu Da; Cheng, Po Yu

doi:10.1109/is3c.2014.122

Cited by 5 publications

(5 citation statements)

References 5 publications

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“…In order to avoid stability issues, a compensation capacitor, C c , was used to ensure that both poles are far enough from each other. The stability criterion considered in this case was to set the output pole at a frequency at least 1.5 times the unity gain frequency of the loop with the aim of obtaining a phase margin of 60 • , mathematically expressed as (12).…”

Section: A Stability Of the Proposed Regulatormentioning

confidence: 99%

“…Applying (12) for a load capacitance of C L = 10 pF, the calculated value of the compensation capacitor that ensures stability at zero load current, calculated according to (13), is C c ≈ 75 fF. The implemented value in the fabricated prototypes was C c = 77 fF.…”

Section: A Stability Of the Proposed Regulatormentioning

confidence: 99%

“…Previous works report the use of super source follower (SSF) structures at the LDO output stage in order to boost the driving capability of the pass transistor, [11], [12], or to optimize the stability [13], [14]. In this work, we propose an alternative scheme consisting of a SSF-based structure, which, to the best of our knowledge, has not been previously proposed in the literature, to perform an adaptive biasing of the EA.…”

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confidence: 99%

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An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

Pereira-Rial

López

Carrillo

et al. 2022

IEEE Trans. Circuits Syst. II

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This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 -11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO's error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.

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Section: A Stability Of the Proposed Regulatormentioning

confidence: 99%

Section: A Stability Of the Proposed Regulatormentioning

confidence: 99%

mentioning

confidence: 99%

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An 11 mA Capacitor-Less LDO With 3.08 nA Quiescent Current and SSF-Based Adaptive Biasing

Pereira-Rial

López

Carrillo

et al. 2022

IEEE Trans. Circuits Syst. II

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“…Battery-powered devices require energy-efficient, highperformance power management integrate circuits (PMICs) with compact size to extend the battery life. Low dropout regulator (LDO)s with low quiescent current (IQ) have been widely used to extend the standby time of such electronic devices, and to generate highprecision, low-noise supplies [1,2,3,4,5,6,7,8,9,10]. However, lower IQ usually leads to poor load transient response.…”

Section: Introductionmentioning

confidence: 99%

“…For capacitor-based LDOs, a source follower buffer is used to push the low frequency pole at the gate of pass device towards the high frequency one to extend bandwidth and ensure stability [20,21,22]. However, the speed of the buffer needs to be fast enough, which means a certain amount of current still needs to be consumed in the buffer.…”

Section: Introductionmentioning

confidence: 99%

Design of 300nA quiescent current and 300mA load capacity LDO with fast transient response

Yu,

Gao,

Zhang

et al. 2024

IEICE Electron. Express

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This paper presents a low dropout regulator (LDO) with a low quiescent current which helps to extend the standby time of battery-powered electronic devices. By utilizing the switchable bias technique in the error amplifier (EA), the bias current is switched to a higher level to accelerate the transient response under heavy load, while a low bias current is applied to EA to maintain a low quiescent current under light load. High speed current comparators and hysteresis control are combined to ensure fast and stable switching operation of the bias current. Moreover, an inrush current suppression circuit is proposed by recycling the switchable bias in EA. During startup, the bias current of EA can be kept low, and a reduced slew rate can be obtained at the pass gate voltage. The proposed LDO has been fabricated in 0.18-μm CMOS process, The experimental total quiescent current is 300nA under no-load condition. The maximum load current is 300mA. Measurement results show that the LDO can be settled within 8μs for a load current step of 0-50mA. In the startup process, the measured inrush current can be effectively limited.

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