Lead free solder bump manufacturing with IBM's C4NP process

Abstract

More and more high-end microelectronic devices are being packaged by using solder bumps as the method of interconnection. The two main technologies used are FlipChip in Package (FCiP) and Wafer Level Chip Scale Package (WLCSP). The main difference is that FCiP devices are placed on a substrate which then interconnects to the PC Board (PCB). WLCSP devices connect directly onto the board.There are various solder bumping technologies used in volume production. These include electroplating, solder paste printing, evaporation and the direct attach of preformed solder spheres. FCiP demands many small bumps on tight pitch whereas WLCSP typically requires much larger solder bumps. All these established technologies have important limitations for fine pitch bumping especially when it comes to lead-free solder alloys. The most commonly used method of generating fine-pitch solder bumps is by electroplating the solder. This process is difficult to control and costly, especially when it comes to lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the European Union to grant exemptions from the ban of lead in certain solder bumping applications. However, the pressure to move to lead-free continues for the entire industry.C4NP (C4-New Process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec. C4NP addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm (or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both, fine-pitch FC in package as well as large pitch / large ball WLCSP bumping applications.This paper provides a summary of manufacturing and reliability results of C4NP bumped high-end logic devices. It discusses the relevant process equipment technology and the novel requirements to run a HVM (high volume manufacturing) C4NP process. Most importantly, the paper describes the achievable bump yields with this new technology. Last but not least, it talks about the C4NP manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques.

Fabrication of a flip chip solder bump using a thin mold and ultrasonic filling

“…In order to fabricate high-quality low-cost solder bumps, Gruber et al [14][15][16] introduced an efficient solder bumping technique, which was called the C4NP (C4 new process). Cavities were made on a thick glass mold by etching, and a molten solder was injected into the cavities of the dewetting mold using the special pressure head.…”

Laser Assisted Solder Bump Mold Fabrication

“…Solder bumping process using a mold has been recently announced for its advantages of good productivity and cost reduction [1][2][3][4][5][6][7]. Generally better results have been achieved when using photolithography for etch mask patterning, yet it is r Cavity highly costly and makes the process too complicated.…”