Lead Zirconium Titanate (PZT)-Based Gate-All-Around Negative-Capacitance Junctionless Nanowire FET for Distortionless Low-Power Applications

Singh, Sarabdeep; Singh, Shradhya; Kumar, Naveen; Singh, Navaneet Kumar; Ranjan, Ravi; Anand, Sunny

doi:10.1007/s11664-021-09277-w

Cited by 5 publications

(4 citation statements)

References 30 publications

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“…At the advanced technology nodes inclusion of high-K gate stacks is essential to eliminate gate leakage and retain the magnitude of ON-current. It has been shown in [51], that Al 2 O 3 gate stack exhibits similar TDDB and Weibull distributions as SiO 2 , even though inherent lattice defects are present in the high-K material. The native oxide thickness (t IL ) is considered for 3 values namely, 0.7 nm, 0.9 nm and 1.3 nm.…”

Section: Dielectric Technology For Mtm Devices: Reliability Aspectmentioning

confidence: 97%

“…In [51], the authors introduced a PZT material-based NC JLNWFET which had an improvement factor of 12.5 in I ON and 6.8 in I ON /I OFF over a JLNWFET. Using 2D materials, a Graphene/CuInP 2 S 6 /MoS 2 MFS vertical heterostructure NWGAA exhibited a minimum SS < 10 mV/dec and average SS < 60 mV/dec for 3 orders of I DS [52].…”

Section: Negative Capacitance Fets-boosting Gaafets Tfets and Finfetsmentioning

confidence: 99%

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More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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The progress in IC miniaturization dictated by Moore’s Law has taken a leap from mere circuit integration to IoT enabled System-on-Chip (SoC) deployments. Such systems are connoted by contemporary advancements in the semiconductor industry roadmaps namely, ‘More-Moore’ and ‘More-than-Moore’ (MtM). For meaningful integration of digital and non-digital blocks, a power performance tradeoff is essential for maximum and fruitful utilization of the silicon area. Using the techniques under the MtM nomenclature allows the use of unconventional steep slope devices like Tunneling FETs, Negative Capacitance (NC) FETs, Gate-all-around FETs (GAA) and FinFETs etc., which can exhibit reasonable performance with lower supply voltages. Following the Device Technology Co-optimization (DTCO) and System Technology Co optimization (STCO) the advanced 3D heterogenous integration technologies allow sensors, analog/mixed signal and passive components to be assimilated within the same package as the CMOS blocks. Appropriate device engineering techniques like multi-gate architectures, vertical stacking transistors, compound semiconductors and alternate carrier transport phenomena are required to improve the current drive and scaling performance of advanced CMOS devices. CMOS based codesign is essential to realize new topologies for energy economical computation, sensing and information processing as the beyond CMOS steep slope devices are independently incapable of replacing conventional bulk CMOS devices. This article presents a detailed qualitative review of the various aspects of MtM beyond CMOS steep slope switches and their prospective integration technologies. For system level integration, various aspects of device performance and optimizations, related device-circuit interactions, dielectric technologies at the advance nanometer nodes have been probed into. Additionally, novel circuit topologies, synthesis algorithms and processor level performance evaluation using steep slope switches have been investigated. An exclusive compact overview for contemporary insights into integrated device-system development methodology and its performance evaluation is presented.

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Section: Dielectric Technology For Mtm Devices: Reliability Aspectmentioning

confidence: 97%

Section: Negative Capacitance Fets-boosting Gaafets Tfets and Finfetsmentioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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“…In 2016, Ali Saeidi and coworkers used PZT in a double-gate NC MOSFET and simulated the 14 nm node ultrathin body and box fully depleted silicon-on-insulator (SOI) FET, and found that SOI-FETs could operate at 0.26 V instead of 0.9 V gate voltage using the NC effect, with an average SS of 55 mV/decade at room temperature, and double gate NC-FETs could operate at 0.24 V with an average SS of 54.5 mV/decade at room temperature [46]. In 2022, Sarabdeep Singh et al simulated a junctionless NWFET with PZT ferroelectric material (NC JLNWFET), and they found that compared with junctionless NWFET without ferroelectric materials (JL NWFET), the NC JLNWFET showed Ion and Ion/Ioff ratio improvement factors of 12.5 and 6.8 respectively [47]. Although promising results have been achieved with conventional ferroelectric materials, the disadvantages of higher deposition temperature, inability to keep polarization intensity large enough with film thickness reduction and incompatibility with CMOS fabrication process limit their further usage in NC-FET devices.…”

Section: ) Ferroelectric Materialsmentioning

confidence: 99%

“…As is known, the NC effect can be integrated in a transistor by simply inserting a ferroelectric material layer in the gate stack, thus the NC effect has the advantage of high compatibility with all kinds of transistor structures. Until now, planar NC-FET, 2D NC-FET, NC-FinFET, NC-TFET, NC GAA-FET and NC GAA-TFET, NC JLGAA-FET [63][64][65][66][67][68][69][70][71][72][73] all have been proposed and experimentally demonstrated with sub-60 mV/dec SS and improved Ion. Besides, the NC effect also proves to be compatible with all kinds of semiconductor channel materials, from 3D Si, Ge, 2D (transition metal dichalcogenides) TMDCs such as MoS2, WSe2, black phosphorus to 1D carbon nanotube.…”

Section: ) Nc-fet Device Typementioning

confidence: 99%

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Qin

Wei

et al. 2023

IEEE Access

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With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor. Hence the Gate all around field effect transistor (GAA-FET) is proposed to replace the Fin field effect transistor (FinFET) in 3 nm technology node and beyond due to its better gate control over the channel with surrounding gate structure, thus providing improved SCE constraint ability. Traditional transistors suffer from the problems of "Boltzmann Tyranny" and cannot overcome the subthreshold swing (SS) limit of 60 mV/dec at room temperature. To maintain high Ion and avoid Ioff from increasing too much, supply voltage (VDD) of the conventional transistor cannot scale down proportionally with the dimension of the transistor. The concept of negative capacitance (NC) has been demonstrated to be able to obtain sub-60 mV/dec SS with the ability of amplifying the potential of the channel region without VDD increment. The novel device structure of negative capacitance gate all around field effect transistor ( NC GAA-FET) can combine both the advantages of GAA-FET and NC-FET, and is the most promising ultra-low power consumption device and promises to sustain the Moore's law further beyond what is predicted now. Whereas, according to our knowledge, there have been few review papers about NC GAA-FET till now. Herein, we summarize the recent advances of the NC GAA-FET both in simulation and experimental aspects, which we believe will bring about profound changes to the further development of NC GAA-FET devices.INDEX TERMS Negative capacitance effect, short channel effect, subthreshold swing, power consumption dissipation, negative capacitance gate all around field effect transistor.

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Dynamic Accumulation Mechanism of Magnetic Abrasive Particles on the Saw Wire Surface

Zhang

2022

Trans. Electr. Electron. Mater.

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Lead Zirconium Titanate (PZT)-Based Gate-All-Around Negative-Capacitance Junctionless Nanowire FET for Distortionless Low-Power Applications

Cited by 5 publications

References 30 publications

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Dynamic Accumulation Mechanism of Magnetic Abrasive Particles on the Saw Wire Surface

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