Leakage current control of nano-scale full adder cells using input vectors

Eratne, Savithra; Nair, Pradeep S.; John, Eugene

doi:10.1109/dtis.2007.4449515

Cited by 5 publications

(6 citation statements)

References 11 publications

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“…Application of body bias to XOR/XNOR gates and full adder circuit reduces the power consumption by increasing the threshold voltage (V ) of individual transistor and thus reducing the leakage currents [3,4]. The single bit full adder circuits have been designed with structured approach as shown in Figure 1 using XNOR/XOR gates and two multiplexer's.…”

Section: System Descriptionmentioning

confidence: 99%

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Low power CMOS full adder design with body biasing approach

Kumar¹,

Arya²,

Pandey³

2020

JICS

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In this paper, five different low power full adders using XOR/XNOR gates and multiplexer blocks with body biasing have been presented. In the first methodology, the adder depicts minimum power dissipation of 204.09μW and delay of 5.9849 ns. In the second, an improvement in power consumption has been reported at 128.92μW with delay of 5.9875 ns by using voltage biasing of two PMOS (P1 &P2) along with substrate biasing. In the third methodology, adder gives minimum power dissipation of 0.223nW with a delay of 5.2352 ns. Further, in fourth, it shows minimum power consumption of 0.199nW with a delay of 5.1002 ns and finally in fifth methodology, minimum power reduces to 0.192nW.Moreover, power delay product (PDP) results also have been compared for these methodologies. Comparisons have been made with earlier reported circuits and proposed circuits show better performance in terms of power consumption and delay.

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Section: System Descriptionmentioning

confidence: 99%

“…Static power is dissipated mainly due to the source and drain leakage currents and controlling the bulk terminal of CMOS device offers improved performance in term of power dissipation and delay. For obtaining low power consumption the transistor has to operate in sub-threshold region [3,4].…”

Section: Introductionmentioning

confidence: 99%

Low power CMOS full adder design with body biasing approach

Kumar¹,

Arya²,

Pandey³

2020

JICS

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“…Sub threshold current is the drain-source current when the gate-source voltage is under the transistor threshold voltage. MOS transistor models predict that when gate-source voltage is at just threshold voltage or below the threshold voltage the transistor does not conduct and there should be is no current flow ideally but practically there is leakage of current [13] will constitute the power called leakage power [11] can it be called as wastage power.…”

Section: Conventional Level Shiftermentioning

confidence: 99%

“…The leakage power of CMOS circuits is determined by the leakage current [12], [13] when the input voltage is less than threshold voltage and transistor is off state (standby mode) but there is leakage of current from Drain to ground. With the development of technology leakage power has become significant component of total power dissipation [8], [9].…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power High Speed Level Shifter

Srinivasulu¹

2014

IJRET

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The leakage power consumption increases with the scaling of the devices and it is expected that the leakage power consumption is important design constraint of total power consumption. In this proposed work , a new configuration of level shifter for low power high speed application has been presented. The proposed circuit ha ve n o cross co u p led con n ection , by which there will be reduction in delay. In this work a new level shifter design has introduced at an ultra low core voltage and has wide range of Input/output voltage. This Low power high speed level shifter allows wide Input/output interface voltage applications in CMOS Technology. On an average it shows an improvement of 8% on average power consumption and 77.2% on delay compared with conventional level shifter with a little bit area overhead.

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“…As supply voltage is scaled down, problems of leakage current,deficient noise margin and small voltage swings arises [5]. Because of shift in technology in submicron region power due to leakage current has become important component of power dissipation [6], [7]. Therefore,static power dissipation has to be given due consideration.…”

mentioning

confidence: 99%

Low power and high speed level shifters in 0.18um technology

Kumar

Moni

Princess

2014

2014 2nd International Conference on Devices, Circuits and Systems (ICDCS)

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As the demand of handheld devices like personal computers,cell phones, multimedia devices etc., is growing, low power consumption has become major design issue for microelectronics circuits. In multi voltage systems, level shifters are significant circuit components and are used in between core circuit and I/O circuit.In this paper high level shifters for low power and high speed application have been presented.Level shifter II has power consumption of 180.75pw and delay of 435.66 us as compared to 231.56 pw and 49.57 ms of level shifter I. Level shifter IV has power consumption of 70.29 pw and delay of 282.87 ps as compared to 77.18 pw and 299.26 ps of level shifter III. All the circuits were simulated using Mentor Graphics Design Architect 0.18um Technology.

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Leakage current control of nano-scale full adder cells using input vectors

Cited by 5 publications

References 11 publications

Low power CMOS full adder design with body biasing approach

Low power CMOS full adder design with body biasing approach

Design of Low Power High Speed Level Shifter

Low power and high speed level shifters in 0.18um technology

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