Leakage in CMOS devices induced by pattern-dependent microloading effect

Wu, Miao; Wang, Winter; Li, Tian; Wu, Chunlei; Fan, Dazhong

doi:10.1109/smelec.2012.6417181

Cited by 5 publications

(2 citation statements)

References 5 publications

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“…Generally, it is found that certain combinations of pattern shape and size can render the structure weak during wafer processing. For example, some special topological structures in chip layout may result in leakage in CMOS devices due to the microloading effect [55]. Similarly, it has been shown that layout attributes such as layout density and feature perimeter sum can be used to compute the post-electroplating topography, modelling the array height, and the step height simultaneously [56].…”

Section: Rule-based Hotspot Analysismentioning

confidence: 99%

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

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Optical projection lithography has been the workhorse of the integrate circuit (IC) manufacturing industry to transfer the computer-aided design (CAD) to semiconducting material wafers. The resolution limit of the 193 nm wavelength lithography which was initially targeted for the 90 nm design rule has been further extended to realise ∼10-20 nm devices with ingenious interventions. The three-dimensional fin-shaped field-effect transistor device structure now realise the <20 nm design rule still using 193 nm projection lithography as the widely accepted solution. The extreme ultraviolet wavelength source systems are still in development and testing phases with some recent success reported, but still falling short of supporting volume production requirements. This study reviews the current trends in lithography and the associated resolution enhancement techniques with brief introduction to an integrated CAD analysis for hotspot detection.

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Section: Rule-based Hotspot Analysismentioning

confidence: 99%

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

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show abstract

“…For example, some special topological structures in the chip layout may result in leakage in CMOS devices due to the micro loading effect [56]. Similarly it has been shown that layout attributes like layout density and feature perimeter sum can be used to compute the post-electroplating topography, modeling the array height and the step height simultaneously [57].…”

Section: A Rule Based Hotspot Analysismentioning

confidence: 99%

Critical Review of Current Trends in ASIC Writing and Layout Analysis

Vikram¹,

Agarwal

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Electrical Designs for Application SpecificIntegrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

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CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication

Vikram

Agarwal

2018

IETE Journal of Research

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Leakage in CMOS devices induced by pattern-dependent microloading effect

Cited by 5 publications

References 5 publications

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Critical Review of Current Trends in ASIC Writing and Layout Analysis

CAD Layout Analysis for Defect Inspection in Semiconductor Fabrication

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