Leakage mechanisms in the trench transistor DRAM cell

Banerjee, Sanjay K.; Coleman, D. J.; Richardson, W. H.; Shah, A.H.

doi:10.1109/16.2425

Cited by 23 publications

(5 citation statements)

References 8 publications

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“…Well-known examples are the injection of carriers into gate oxides of metal-oxide-semiconductor-fieldeffect-transistors ͑MOSFETs͒ 1,2 leading to a long-term shift of their threshold voltage ͑so-called degradation͒, the strong tunnel currents during the erase mode of electrically erasable programmable read only memories ͑EPROMs͒, 3 the currentvoltage characteristics of metal-insulator-semiconductor ͑MIS͒ solar cells, [4][5][6][7] or the tunneling leakage occurring in memory cells. 8,9 Modeling and numerical simulation of these currents rely not only on realistic distribution functions for the charge carriers, but also on a good knowledge of the quantum-mechanical transmission probability for ultra-thin barriers.…”

Section: Introductionmentioning

confidence: 99%

Modeling and simulation of tunneling through ultra-thin gate dielectrics

Schenk¹,

Heiser

1997

Journal of Applied Physics

213

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Direct and Fowler-Nordheim tunneling through ultra-thin gate dielectrics is modeled based on an approach for the transmission coefficient ͑TC͒ of a potential barrier that is modified by the image force. Under the constraint of equal actions the true barrier is mapped to a trapezoidal pseudobarrier resulting in a TC very close to the numerical solution of the Schrödinger equation for all insulator thicknesses and for all energies of the tunneling electron. The barrier height of the pseudopotential is used as a free parameter and becomes a function of energy in balancing the actions. This function can be approximated by a parabolic relation which makes the TC of arbitrary barriers fully analytical with little loss of accuracy. The model was implemented into a multidimensional device simulator and applied to the self-consistent simulation of gate currents in metal-oxide-semiconductor ͑MOS͒ capacitors with gate oxides in the thickness range 15 Å-42 Å. Excellent agreement with experimental data was obtained using a thickness-independent tunnel mass m ox ϭ0.42 m 0. Thanks to the CPU-time efficiency of the method the simulation of a complete MOS-field-effect-transistor with dominating gate current becomes possible and shows the potential for further applications.

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Section: Introductionmentioning

confidence: 99%

Modeling and simulation of tunneling through ultra-thin gate dielectrics

Schenk¹,

Heiser

1997

Journal of Applied Physics

213

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“…= h2k 2,/2Ix r the transverse part of the kinetic energy, and kli the k-component parallel to the field direction. The integration variable kll is scaled by a factor eF/hOr in the third-power terms of the exponential in (30), which cuts the k,-integration due to rapid oscillations of the integrand just for very small kll-values. The last assertion is a consequence of the general constraint to the field strength:…”

Section: Direct (Zero Phonon ) Transitionsmentioning

confidence: 99%

“…Del Alamo and Swanson [21] pointed out, that as scaling advances, tunneling must be expected at the whole emitter-base area posing a principal limit to the gain. Various papers [22][23][24][25][26][27] dealt with drain-substrate tunneling leakage in MOSFETs and its reduction, with hot carrier injection across the gate oxide initiated by tunneling generation [28,29], and with tunneling leakage in trench transistor DRAM cells [30,31]. In all these papers either band-to-band tunneling or tunneling via bulk or surface traps was considered the leakage mechanism.…”

Section: Introductionmentioning

confidence: 99%

Rigorous theory and simplified model of the band-to-band tunneling in silicon

Schenk¹

1993

Solid-State Electronics

197

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The phonon-assisted band-to-band tunneling rate in crystalline silicon is calculated using the equilibrium Green's function formalism. Electron-phonon collisions, that balance the momentum, are included in the perturbation operator. Houston-type solutions are used for the time dependence of the Bloch states. RPA deeoupling yields a tractable expression for the differential tunneling conductivity. Its evaluation is presented explicitly, taking exactly into account the anisotropy of the six conduction band valleys. A simplified rate formula for the purpose of device simulation is then derived from the general expression, restricting the field strength and using reasonable models for the matrix elements. It is shown that indirect, phonon-assisted tunneling largely exceeds direct tunneling at all events. Finally, band-toband tunneling is compared with trap-assisted tunneling. We conclude that the pre-breakdown range in silicon is dominated by tunneling via traps.

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“…First concerns about the impact of BTBT leakage current in scaled technologies were reported for base-emitter junctions in bipolar transistors, 47 followed by trench transistors for DRAM cells. 48 The introduction of halo implants also raised the issue for CMOS technologies. 49 The BTBT current is usually modeled following the original approach by Kane, 50 yielding a general expression 51…”

Section: Introductionmentioning

confidence: 99%

High Doping Density/High Electric Field, Stress and Heterojunction Effects on the Characteristics of CMOS Compatible p-n Junctions

Simoen

Eneman

González

et al. 2011

J. Electrochem. Soc.

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This paper critically reviews the different mechanisms impacting the current-voltage and capacitance voltage characteristics of complementary metal oxide semiconductor (CMOS) compatible p-n junctions. Special attention is given to the influence of high doping density=high electric fields, mechanical stress and the presence of a hetero-junction either at the junction or in the depletion region. The basic mechanisms reported in the literature are checked for their validity for state-of-the-art structures and processing techniques. Critical issues are pointed out and illustrated for advanced CMOS compatible hetero-junctions, where high-field effects, like trap-assisted tunneling (TAT) and band-to-band-tunneling (BTBT) play a prominent role. The presence of an isotype hetero-junction gives rise to frequency dispersion in the depletion layer capacitance, which becomes more pronounced in combination with grown-in or processing-induced defects at the hetero-interface. Finally, the challenges and opportunities for future devices are addressed.

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Leakage mechanisms in the trench transistor DRAM cell

Cited by 23 publications

References 8 publications

Modeling and simulation of tunneling through ultra-thin gate dielectrics

Modeling and simulation of tunneling through ultra-thin gate dielectrics

Rigorous theory and simplified model of the band-to-band tunneling in silicon

High Doping Density/High Electric Field, Stress and Heterojunction Effects on the Characteristics of CMOS Compatible p-n Junctions

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