Leakage Power Analysis in Different S-Box Masking Protection Schemes

Bahrami, Javad; Ebrahimabadi, Mohammad; Danger, Jean‐Luc; Guilley, Sylvain; Karimi, Naghmeh

doi:10.23919/date54114.2022.9774763

Cited by 8 publications

(4 citation statements)

References 23 publications

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“…Aging mechanisms result in performance degradation and eventual failure of digital circuits over time. In CMOS technology, the two leading factors of aging are Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) [2]. Both mechanisms result in increasing switching voltage and path delays.…”

Section: A Background On Device Agingmentioning

confidence: 99%

“…Both mechanisms result in increasing switching voltage and path delays. NBTI (one class of BTI) [2] affects PMOS transistors, while PBTI (another class of BTI) as well as HCI affects NMOS devices. BTI Aging: A PMOS (NMOS) transistor goes under two phases of NBTI (PBTI) depending on its operating condition [2].…”

Section: A Background On Device Agingmentioning

confidence: 99%

“…NBTI (one class of BTI) [2] affects PMOS transistors, while PBTI (another class of BTI) as well as HCI affects NMOS devices. BTI Aging: A PMOS (NMOS) transistor goes under two phases of NBTI (PBTI) depending on its operating condition [2]. The first phase, i.e., stress, occurs when the related transistor is "ON".…”

Section: A Background On Device Agingmentioning

confidence: 99%

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Special Session: Security Verification & Testing for SR-Latch TRNGs

Bahrami

Ebrahimabadi

Danger

et al. 2023

2023 IEEE 41st VLSI Test Symposium (VTS)

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Secure chips implement cryptographic algorithms and protocols to ensure self-protection (e.g., firmware authenticity) as well as user data protection (e.g., encrypted data storage). In turn, cryptography needs to defer to incorruptible sources of entropy to implement their functions according to their mandatory usage guidance. Typically, keys, nonces, initialization vectors, tweaks, etc. shall not be guessed by attackers. In practice, True Random Number Generators (TRNGs) are in charge of producing such sensitive elements.Fully aware of the central role of TRNGs in the proper implementation of security in chips, stakeholders have been formalizing the requirements recently. The methods to strengthen such requirements are manifold. In this paper, we discuss and apply three of them by targeting the Set-Reset Latch TRNG which is an alternative to Ring-Oscillator (RO) TRNGs as it provides faster throughputs. The first method concerns the confidence in the TRNG being random enough. It explores how the TRNG properties can be reliably predicted by simulation, compared to real silicon experiments. The second aspect dealt with in this paper is the assessment of the TRNG properties over time, i.e., considering the impact of aging in the TRNG properties. Such knowledge is important as secure chips are expected to be in service for a long period, and it would be detrimental to the service they render if the quality of the entropy they deliver would be declining over time. Eventually, the third aspect of this paper is the timely detection of unforeseen failures or malevolent attacks. The mitigation lies in leveraging "health tests" launched prior to using random numbers.This paper focuses on a particular type of TRNG that is not prone to biasing by attackers: it is the so-called Set-Reset Latch (SR-latch) TRNG and exploits a race condition in an arbitration gate. Such kind of TRNG is of great practical interest as an alternative design compared to the mainstream "Ring Oscillator" TRNG, and it is also very amenable to analyses by various sorts of simulations aiming at properly characterizing its security in various operational environments.

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Section: A Background On Device Agingmentioning

confidence: 99%

Section: A Background On Device Agingmentioning

confidence: 99%

See 1 more Smart Citation

Special Session: Security Verification & Testing for SR-Latch TRNGs

Bahrami

Ebrahimabadi

Danger

et al. 2023

2023 IEEE 41st VLSI Test Symposium (VTS)

Self Cite

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“…NMOS) transistor goes under two phases of NBTI (resp. PBTI) depending on its operating condition [2]. The first phase, i.e., stress, occurs when the related transistor is "ON".…”

Section: Background On Device Agingmentioning

confidence: 99%

Challenges in Generating True Random Numbers Considering the Variety of Corners, Aging, and Intentional Attacks

Bahrami,

Danger,

Ebrahimabadi

et al. 2023

2023 International Conference on IC Design and Technology (ICICDT)

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True Random Number Generators (TRNGs) are sensitive Intellectual Property (IP) blocks involved in the creation of cryptographic keys, initialization vectors, nonces, etc. They must behave properly within a large environmental spectrum, including multiple corners, in case of aging-induced change of device characteristics over time, and also under intentional attacks aiming at lowering the TRNGs entropy.In this paper, we review normative and technical landscapes in this respect, and propose a pre-silicon verification methodology to assess the resilience of TRNGs. In particular, we qualify the unitary free running oscillator (FRO) entropy source analytically, and then extend the study to a full FRO-based IP module. Our results encompass analytical characterizations in terms of jitter measurements and certification-based characterizations in terms of tests.

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Multi-modal Pre-silicon Evaluation of Hardware Masking Styles

Anik,

Reefat,

Cheng

et al. 2024

J Electron Test

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Protecting sensitive logic functions in ASICs requires side-channel countermeasures. Many gate-level masking styles have been published, each with pros and cons. Some styles such as RSM, GLUT, and ISW are compact but can feature 1st-order leakage. Some other styles, such as TI, DOM, and HPC are secure at the 1st-order but incur significant overheads in terms of performance. Another requirement is that security shall be ensured even when the device is aged. Pre-silicon security evaluation is now a normatively approved method to characterize the expected resiliency against attacks ahead of time. However, in this regard, there is still a fragmentation in terms of leakage models, Points of Interest (PoI) selection, attack order, and distinguishers. Accordingly, in this paper we focus on such factors as they affect the success of side-channel analysis attacks and assess the resiliency of the state-of-the-art masking styles in various corners. Moreover, we investigate the impact of device aging as another factor and analyze its influence on the success of side-channel attacks targeting the state-of-the-art masking schemes. This pragmatic evaluation enables risk estimation in a complex PPA (Power, Performance, and Area) and security plane while also considering aging impacts into account. For instance, we explore the trade-off between low-cost secure styles attackable at 1st-order vs high-cost protection attackable only at 2nd-order.

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Leakage Power Analysis in Different S-Box Masking Protection Schemes

Abstract: County (UMBC) ScholarWorks@UMBC digital repository on the Maryland Shared Open Access (MD-SOAR) platform.

Cited by 8 publications

References 23 publications

Special Session: Security Verification & Testing for SR-Latch TRNGs

Special Session: Security Verification & Testing for SR-Latch TRNGs

Challenges in Generating True Random Numbers Considering the Variety of Corners, Aging, and Intentional Attacks

Multi-modal Pre-silicon Evaluation of Hardware Masking Styles

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