Leakage Reduction Technique and Analysis of CMOS D Flip Flop

Abstract

Power consumption and delay are the two major issues in the design of today's VLSI based battery operated portable electronic devices. Memory units in these devices are made of flip flops and each flip flop will consume more power in both active and idle conditions. Through this paper we try to explore alternate techniques to implement D flip-flop with the aim of reducing leakage power, delay and to increase the speed. All the different configurations of D flip-flops are simulated using HSPICE in 90nm process technology with BSIM4 MOS transistor models of level 54.