Leakage Resilience against Concurrent Cache Attacks

Barthe, Gilles; Köpf, Boris; Mauborgne, Laurent; Ochoa, Martín

doi:10.1007/978-3-642-54792-8_8

Cited by 26 publications

(18 citation statements)

References 21 publications

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“…However, allowing a limited number of crashes with the same key will bound the information that an adversary can gain. For instance, leakage resilient cryptography has been sucessfully applied to real implementations in the case of side-channels caused by CPU caches [5]. Alternatively, bounds on the leakage could be obtained by leveraging on quantitative estimations on implementations using techinques such as [28].…”

Section: Attack-resistance Of Isrmentioning

confidence: 99%

Short Paper

Bănescu

Ochoa

2015

Proceedings of the 10th ACM Workshop on Programming Languages and Analysis for Security

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In this paper, we introduce a formal notion of partial compliance, called ATTACK-RESISTANCE, of a computer program running together with a defense mechanism w.r.t a non-exploitability specification. In our setting, a program may contain exploitable vulnerabilities, such as buffer overflows, but appropriate defense mechanisms built into the program or the operating system render such vulnerabilities hard to exploit by certain attackers, usually relying on the strength of the randomness of a probabilistic transformation of the environment or the program and some knowledge on the attacker's goals and attack strategy. We are motivated by the reality that most large-scale programs have vulnerabilities despite our best efforts to get rid of them. Security researchers have responded to this state of affairs by coming up with ingenious defense mechanisms such as address space layout randomization (ASLR) or instruction set randomization (ISR) that provide some protection against exploitation. However, implementations of such mechanism have been often shown to be insecure, even against the attacks they were designed to prevent. By formalizing this notion of attackresistance we pave the way towards addressing the questions: "How do we formally analyze defense mechanisms? Is there a mathematical way of distinguishing effective defense mechanisms from ineffective ones? Can we quantify and show that these defense mechanisms provide formal security guarantees, albeit partial, even in the presence of exploitable vulnerabilities?". To illustrate our approach we discuss under which circumstances ISR implementations comply with the ATTACK-RESISTANCE definition.

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Section: Attack-resistance Of Isrmentioning

confidence: 99%

Short Paper

Bănescu

Ochoa

2015

Proceedings of the 10th ACM Workshop on Programming Languages and Analysis for Security

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“…in the non-concurrent attacker model. A follow-up [14] provides an upper bound for the leakage of AES in the concurrent attacker model; the result is stated in an abstract setting, and under some restrictions. The results of [14] cannot be used to assert the security of constant-time programs against concurrent cache attacks.…”

Section: Related Workmentioning

confidence: 99%

System-level Non-interference for Constant-time Cryptography

Barthe

Betarte

Campo

et al. 2014

Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications Security

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122

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Abstract. Cache-based attacks are a class of side-channel attacks that are particularly effective in virtualized or cloud-based environments, where they have been used to recover secret keys from cryptographic implementations. One common approach to thwart cache-based attacks is to use constant-time implementations, i.e. which do not branch on secrets and do not perform memory accesses that depend on secrets. However, there is no rigorous proof that constant-time implementations are protected against concurrent cache-attacks in virtualization platforms with shared cache; moreover, many prominent implementations are not constant-time. An alternative approach is to rely on system-level mechanisms. One recent such mechanism is stealth memory, which provisions a small amount of private cache for programs to carry potentially leaking computations securely. Stealth memory induces a weak form of constant-time, called S-constant-time, which encompasses some widely used cryptographic implementations. However, there is no rigorous analysis of stealth memory and S-constant-time, and no tool support for checking if applications are S-constant-time. We propose a new information-flow analysis that checks if an x86 application executes in constant-time, or in S-constant-time. Moreover, we prove that constant-time (resp. S-constant-time) programs do not leak confidential information through the cache to other operating systems executing concurrently on virtualization platforms (resp. platforms supporting stealth memory). The soundness proofs are based on new theorems of independent interest, including isolation theorems for virtualization platforms (resp. platforms supporting stealth memory), and proofs that constant-time implementations (resp. S-constant-time implementations) are non-interfering with respect to a strict information flow policy which disallows that control flow and memory accesses depend on secrets. We formalize our results using the Coq proof assistant and we demonstrate the effectiveness of our analyses on cryptographic implementations, including PolarSSL AES, DES and RC4, SHA256 and Salsa20.

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“…those that can control and observe the cache state before and after, but not during, the execution of the victim program. A description of CacheAudit's support for concurrent, asynchronous access-based adversaries as in [104] can be found in [84].…”

Section: Side-channelsmentioning

confidence: 99%

“…One of our prime targets for future work is to derive security guarantees that hold for multiple executions of the victim process. One possibility to achieve this is to employ leakage-resilient cryptosystems [81,82], where our work can be used to bound the range of the leakage functions, as demonstrated in [84].…”

Section: Meaning Of Boundsmentioning

confidence: 99%

“…Most works in that direction consider physical sidechannel attacks such as analysis of power and electromagnetic radiation. For reasoning about cache-based attacks, Barthe et al [84] propose an extension to CacheAudit (see Chapter 5), which allows reasoning about leakage-resilient cryptosystems, for concurrent access-based cache adversaries.…”

Section: Leakage-resilient Cryptographymentioning

confidence: 99%

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Tools for the Evaluation and Choice of Countermeasures against Side-Channel Attacks

Doychev¹

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Side-channel attacks have been successful in breaking cryptographic protections of systems, by using secret-dependent variations of non-functional properties such as timing or traffic volume. Countermeasures against side-channel attacks usually attempt to eliminate or reduce these variations, which may lead to performance penalties such as increases in the running time of programs, or in the traffic volume they induce. This thesis investigates the trade-off between the security of side-channel countermeasures, and their cost in terms of performance penalties. For this, we seek rigorous answers to two research questions:Q1: How to choose a balance between the security guarantees and the performance penalties of side-channel countermeasures? Q2: How to measure the security of side-channel countermeasures on practical systems? This thesis develops tools that enable the security quantification and the choice of practical countermeasures against side-channel attacks. These tools include the necessary formal models, as well as algorithms and software tools to allow the automatic evaluation of practical systems.In addressing Q1, we develop the first systematic approach for choosing side-channel countermeasures. We do this in a game-theoretic model, where a defender chooses a protection against an adversary who performs an attack. We apply this approach for reasoning about countermeasures against timing attacks, i.e., attacks where an adversary can exploit secret-dependent execution time of programs. We identify cases where leaky countermeasures are preferable to leak-free, constant-time implementations, as they offer better performance without sacrificing security.In addressing Q2, we develop the first tools for the automatic formal quantification of the security of side-channel countermeasures in practical systems. We do this for two types of attacks: cache attacks, where an adversary exploits secret-dependent timing differences due to the use of the CPU cache, and web-traffic attacks, where an adversary exploits secret-dependent differences in the volume of encrypted traffic.To capture cache attacks, we develop the tool CacheAudit, which performs static analysis of x86 binaries, and quantifies their security with respect to cache adversaries. Using CacheAudit, we analyze implementations of AES from the PolarSSL library, as well as of the finalists of the eSTREAM stream cipher competition, and we reason about the effects of architectural features such as cache size and replacement policy to side-channel leakage. Furthermore, we devise novel techniques that provide support for bit-level and symbolic reasoning about pointers in the presence of dynamic memory allocation, which we apply for reasoning about the effectiveness of several widely deployed side-channel countermeasures from the libgcrypt and OpenSSL libraries.To capture web-traffic attacks, we develop scalable algorithms that enable the formal quantification of web-traffic leakage, as well as the generating of provable protections. We apply these algorit...

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Leakage Resilience against Concurrent Cache Attacks

Cited by 26 publications

References 21 publications

Short Paper

Short Paper

System-level Non-interference for Constant-time Cryptography

Tools for the Evaluation and Choice of Countermeasures against Side-Channel Attacks

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