Learning-based power modeling of system-level black-box IPs

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Zhang

2019

As field-programmable gate arrays become prevalent in critical application domains, their power consumption is of high concern. In this paper, we present and evaluate a power monitoring scheme capable of accurately estimating the runtime dynamic power of FPGAs in a fine-grained timescale, in order to support emerging power management techniques. In particular, we describe a novel and specialized ensemble model which can be decomposed into multiple customized decision-tree-based base learners. To aid in model synthesis, a generic computer-aided design flow is proposed to generate samples, select features, tune hyperparameters and train the ensemble estimator. Besides this, a hardware realization of the trained ensemble estimator is presented for on-chip real-time power estimation. In the experiments, we first show that a single decision tree model can achieve prediction error within 4.51% of a commercial gate-level power estimation tool, which is 2.41-6.07× lower than provided by the commonly used linear model. More importantly, we study the extra gains in inference accuracy using the proposed ensemble model. Experimental results reveal that the ensemble monitoring method can further improve the accuracy of power predictions to within a maximum error of 1.90%. Moreover, the lookup table (LUT) overhead of the ensemble monitoring hardware employing up to 64 base learners is within 1.22% of the target FPGA, indicating its lightweight and scalable characteristics.

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An Ensemble Learning Approach forIn-SituMonitoring of FPGA Dynamic Power

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Zhang

2019

“…Work [8], [9] extracted the toggle rate of a small set of internal signals and built the model in embedded processors, resulting in the LUT resource overhead of 7% in [8] and 9% in [9] for their tested applications, as well as around 5% CPU time for both of these two work. Furthermore, as studied in [10], [11], power behaviors of complex arithmetic units are generally non-linear. Hence, the linear model exhibits intrinsic restriction in accuracy enhancement when non-linear power patterns increase with the growing sample size, which is known as the underfitting problem in machine learning theory.…”

Section: Related Workmentioning

confidence: 99%

“…The average MAE percentage is 4.36% for our proposed decision tree model whereas the linear regression indicates an average error of 17.31%. From Table II, we can see that the advantages of decision tree over linear model is larger for DSP-based and hybrid designs, because the LUTs are intrinsically better to be fitted in the linear regression model while the DSPs are inclined to have non-linear power patterns, as reported in [10], [11] that the complex arithmetic units generally exhibit non-linear power behaviors.…”

Section: A Model Assessmentmentioning

confidence: 99%

Decision tree based hardware power monitoring for run time dynamic power management in FPGA

Zhang

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

2017

Fine-grained runtime power management techniques could be promising solutions for power reduction. Therefore, it is essential to establish accurate power monitoring schemes to obtain dynamic power variation in a short period (i.e., tens or hundreds of clock cycles). In this paper, we leverage a decision-tree-based power modeling approach to establish finegrained hardware power monitoring on FPGA platforms. A generic and complete design flow is developed to implement the decision tree power model which is capable of precisely estimating dynamic power in a fine-grained manner. A flexible architecture of the hardware power monitoring is proposed, which can be instrumented in any RTL design for runtime power estimation, dispensing with the need for extra power measurement devices. Experimental results of applying the proposed model to benchmarks with different resource types reveal an average error up to 4% for dynamic power estimation. Moreover, the overheads of area, power and performance incurred by the power monitoring circuitry are extremely low. Finally, we apply our power monitoring technique to the power management using phase shedding with an on-chip multi-phase regulator as a proof of concept and the results demonstrate 14% efficiency enhancement for the power supply of the FPGA internal logic.

“…Specifically, we propose HL-Pow, a learning-based power modeling framework for HLS designs. Our modeling framework features wide applicability and high efficiency compared with state-of-the-art works [10]- [13]. First of all, HL-Pow offers a modeling strategy with high generalization ability so that various designs can use one well developed model for power prediction without the need of model reconstruction when targeting the same FPGA platform.…”

Section: Introductionmentioning

confidence: 99%

HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis

Zhao

2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)

et al. 2020

High-level synthesis (HLS) enables designers to customize hardware designs efficiently. However, it is still challenging to foresee the correlation between power consumption and HLS-based applications at an early design stage. To overcome this problem, we introduce HL-Pow, a power modeling framework for FPGA HLS based on state-of-the-art machine learning techniques. HL-Pow incorporates an automated feature construction flow to efficiently identify and extract features that exert a major influence on power consumption, simply based upon HLS results, and a modeling flow that can build an accurate and generic power model applicable to a variety of designs with HLS. By using HL-Pow, the power evaluation process for FPGA designs can be significantly expedited because the power inference of HL-Pow is established on HLS instead of the time-consuming registertransfer level (RTL) implementation flow. Experimental results demonstrate that HL-Pow can achieve accurate power modeling that is only 4.67% (24.02 mW) away from onboard power measurement. To further facilitate power-oriented optimizations, we describe a novel design space exploration (DSE) algorithm built on top of HL-Pow to trade off between latency and power consumption. This algorithm can reach a close approximation of the real Pareto frontier while only requiring running HLS flow for 20% of design points in the entire design space.