Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems

Abstract

Abstract-Embedded systems execute applications with varying performance requirements. These applications exercise the hardware differently depending on the computation task, generating varying workloads with time. Energy minimization with such workload and performance variations within (intra) and across (inter) applications is particularly challenging. To address this challenge we propose an online approach, capable of minimizing energy through adaptation to these variations. At the core of this approach is a reinforcement learning algorithm that suitably selects the appropriate voltage/frequency scaling (VFS) based on workload predictions to meet the applications' performance requirements. The adaptation is then facilitated and expedited through learning transfer, which uses the interaction between the application, runtime and hardware layers to adjust the VFS. The proposed approach is implemented as a power governor in Linux and extensively validated on an ARM Cortex-A8 running different benchmark applications. We show that with intraand inter-application variations, our proposed approach can effectively minimize energy consumption by up to 33% compared to the existing approaches. Scaling the approach to multi-core systems, we also demonstrate that it can minimize energy by up to 18% with 2X reduction in the learning time when compared with an existing approach.

Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores

“…For performing all the processing at run-time, several works have been reported [8], [15], [16], [22]- [24]. In [22], the online algorithm utilizes hardware performance monitoring counters (PMCs) to achieve energy savings without recompiling the applications.…”

“…Here, we consider three applications having different workloads from SPLASH: fmm (fm), radix (rd) and raytrace (ra), and their respective combinations fm-rd, fm-ra, rd-ra and fm-rd-ra. The metric considered to classify the workload is Memory Reads Per Instruction (MRPI= L2 cache read refills instructions retired ) as opposed to the more commonly used CPU cycles [8] for classifying the application workloads. Selection of MRPI is influenced by its relatively low overhead (two performance counters only) and high correlation with the memory intensiveness of an application.…”

“…Subsequently, it monitors the workload prediction error and performance loss, quantified by instructions per second (IPS) at runtime and adjusts the chosen V-f to compensate. The proposed approach shifts heavy computations to offline and thus helps in reducing the runtime overheads compared to learning-based approaches [8], [16]. The proposed approach is validated on the Odroid-XU3 platform with the various combinations of applications from PARSEC and SPLASH benchmarks.…”

Machine learning for run-time energy optimisation in many-core systems

“…The reward function R i at t i (4) is computed as a function of the resulting average slack ratio at the t i -th decision epoch (Li) and its change since the last decision epoch The T i can be calculated as the ratio of the observed processor cycles and the chosen operating frequency at the i-th decision epoch [12].…”

“…The framework is based upon the Reinforcement Learning (RL) approach described in [11], [12]. The framework invokes workload prediction and appropriate V-F control to achieve energy minimisation for applications executed on a multi-core hardware platform.…”