LEON3 ViP: A Virtual Platform with Fault Injection Capabilities

Abstract

In addition to functional simulation for validation of hardware/software designs, there are additional robustness requirements that need advanced simulation techniques and tools to analyze the system behavior in the presence of faults. In this paper, we present the design of a fault injection framework for LEON3, a 32bit SPARC CPU based system used by the European Space Agency, described at Transaction Level using SystemC. First of all an extension of a previous XML formalization of basic binary faults, like memory and CPU registers corruption, is done in order to support TLM2.0 transaction's parameters corruptions. Next a novel Dynamic Binary Instrumentation (DBI) technique for C++ binaries is used to insert fault injection wrappers in SystemC transaction path. For binary faults in model components the use of TLM2.0 "transport_dbg" is proposed. This way each component with fault injection capabilities exposes a standard interface to allow internal component inspection and modification.

Non-intrusive fault tolerance in soft processors through circuit duplication

“…The VHDL model is fully synthesizable with most synthesis tools and can be implemented in both FPGAs and ASICs. Simulation can be done with all VHDL-S7 compliant simulators [10]. In order to use the LEON3 soft-processor embedded on a COTS SRAM FPGA aiming an OBC for satellites it is necessary to improve the processor mitigation with a fault tolerance technique.…”

“…Several simulation-based techniques have been developed [10] [15] and could be used to estimate SEU sensitivity in the proposed aBC architecture. However, complex projects with hundreds of thousands of gates would represent a huge amount of fault possibilities, and the capability of analyzing a significant number of faults may not be realistic.…”

OpenPiton

“…Consequently, metrics such as architectural vulnerability factor (AVF), failures in time (FIT), and mean time to failure (MTTF) can be estimated. Many studies [25,26,48,60,61,89] have used open source processors to perform fault injection. They have also been used in thermal and power management reliability modeling [33,35] as well as wearout fault modeling studies [74].…”

A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems

“…A large number of fault injectors for digital systems has been proposed in the past years, as shown in the survey presented in [2]. Based on the goal we pursue, the most relevant aspect for their classification is the abstraction level they work at: physical fault injection (e.g., [12,13]), software implemented fault injection (SWIFI, e.g., [14,15]), fault emulation (e.g., [5,8,6,4,16]), or fault simulation (e.g., [11,3,7,[17][18][19][20][21]). Since they act at different abstraction levels, the various approaches are complementary, and, therefore, they support the reliability analysis in the various phases of the system design flow, from the preliminary evaluation towards the final system validation.…”