Lessons from at-speed scan deployment on an Intel&amp;#x00AE; Itanium&amp;#x00AE; microprocessor

Pant, Pankaj; Zelman, Joshua; Colon-Bonet, Glenn; Flint, Jennifer; Yurash, Steve

doi:10.1109/test.2010.5699256

Cited by 13 publications

(12 citation statements)

References 16 publications

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“…Unlike this paper, [12] focuses solely on the processor core, describing capabilities such as stalling the pipeline. The authors of [14][15][16] describe debugging mechanisms and their usage methodology, but do so in the realm of manufacturing testing. The authors of [14][15][16] describe debugging mechanisms and their usage methodology, but do so in the realm of manufacturing testing.…”

Section: Related Workmentioning

confidence: 99%

Debugging post-silicon fails in the IBM POWER8 bring-up lab

Dusanapudi¹,

Fields²,

Floyd³

et al. 2015

IBM J. Res. & Dev.

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Debugging post-silicon fails continues to be a difficult problem that is becoming even more challenging as chips integrate more functionality and implement increasingly complicated functions. Additionally, the complexity of hardware systems, coupled with the difficulty in observing the state of the system that led to the failure, make the debugging effort a unique challenge. In this paper, we review the techniques and mechanisms used to facilitate effective debugging in the POWER8i processor post-silicon validation phase. We further describe several functional bugs and describe the debugging process that drove the identification of their root cause.

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Section: Related Workmentioning

confidence: 99%

Debugging post-silicon fails in the IBM POWER8 bring-up lab

Dusanapudi¹,

Fields²,

Floyd³

et al. 2015

IBM J. Res. & Dev.

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“…On the other hand, the robustness of the power delivery system also determines the developing time and the recovering time of the supply voltage droop. When the circuit experiences a sudden change of switching activity, a power network with poor current delivery capacity will suffer from faster first voltage droop event and it will take longer time to recover [12]. Consequently, the at-speed scan patterns are more prone to fail at the clock frequency lower than the functional mode when they have higher switching activity.…”

Section: Figmentioning

confidence: 99%

Power Supply Droop and Its Impacts on Structural At-Speed Testing

Lin

2012

2012 IEEE 21st Asian Test Symposium

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Scan based at-speed testing has become mandatory in industry to detect delay defects today in order to maintain test quality and reduce test cost. However, the effects of power supply droop during test application often introduce timing uncertainty, such as clock stretch and additional gate delay. It leads to false failure and test escape during test and makes the application of the at-speed scan testing become a challenge task to screen out delay defects successfully. In this paper, we review existing studies about the power supply droop and the methods to reduce its impact on at-speed scan testing.

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“…This excessive peak power in LOS scheme, leads to high voltage droop on the power grid, more than what the power grid is designed to handle. This excessive voltage droop specific to test mode, can lead to false delay failures, thereby leading to significant yield reduction [et al 2003;Girard et al 2009;Pant et al 2010], that is unwarranted. In [Liu 2004], it was shown that transition fault testing can be performed with stuck fault patterns, with 46% lesser test time, if combinational state preservation (CSP) property can be satisfied in scan-shift mode.…”

Section: Introductionmentioning

confidence: 99%

Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing

Trinadh

Potluri

Babu

et al. 2017

ACM Trans. Des. Autom. Electron. Syst.

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Due to the increase in manufacturing/environmental uncertainties in the nanometer regime, testing digital chips under different operating conditions becomes mandatory. Traditionally, stuck-at tests were applied at slow speed to detect structural defects and transition fault tests were applied at-speed to detect delay defects. Recently, it was shown that certain cell-internal defects can only be detected using at-speed stuck-at testing. Stuck-at test patterns are power hungry, thereby causing excessive voltage droop on the power grid, delays the test response and finally leading to false delay failures on the tester. This motivates the need for peak power minimization during at-speed stuck-at testing. In this paper, we use input toggle minimization as a means to minimize circuit's power dissipation during at-speed stuck-at testing under the CSP-scan DFT scheme. For circuits whose test sets are dominated by don't cares, this paper maps the problem of optimal X-filling for peak input toggle minimization to a variant of interval coloring problem and proposes a dynamic programming (DP) algorithm (DP-fill) for the same along with a theoretical proof for its optimality. For circuits whose test sets are not dominated by don't cares, we propose a max scatter Hamiltonian path algorithm, which ensures that the ordering is done such that the don't cares are evenly distributed in the final ordering of test cubes, thereby leading to better input toggle savings than DP-fill. The proposed algorithms, when experimented on ITC99 benchmarks, produced peak power savings of up to 48% over the best known algorithms in literature. We have also pruned the solutions thus obtained, using Greedy and Simulated Annealing strategies with iterative 1-bit neighborhood, to validate our idea of optimal input toggle minimization as an effective technique for minimizing peak power dissipation during at-speed stuck-at testing.

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Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor

Cited by 13 publications

References 16 publications

Debugging post-silicon fails in the IBM POWER8 bring-up lab

Debugging post-silicon fails in the IBM POWER8 bring-up lab

Power Supply Droop and Its Impacts on Structural At-Speed Testing

Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing

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