Let’s Tessellate: Tiling for Security Against Advanced Probe and Fault Adversaries

Dhooghe, Siemen; Nikova, Svetla

doi:10.1007/978-3-030-68487-7_12

Cited by 2 publications

(1 citation statement)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…(3) The view generated with regard to the inputs must be consistent with the output in the real world. For instance, for a gadget, this has been well-formulated in [70]. The adversary (also called "distinguisher") interacts with the real gadget in the real world, and a simulator mimics its interaction.…”

Section: Probing Modelmentioning

confidence: 99%

Circuit Masking: From Theory to Standardization, A Comprehensive Survey for Hardware Security Researchers and Practitioners

Covic,

Ganji,

Forte

2021

Preprint

View full text Add to dashboard Cite

Side-channel attacks extracting sensitive data from implementations have been considered a major threat to the security of cryptographic schemes. This has elevated the need for improved designs by embodying countermeasures, with masking being the most prominent example. To formally verify the security of a masking scheme, numerous attack models have been developed to capture the physical properties of the information leakage as well as the capabilities of the adversary. With regard to these models, extensive research has been performed to realize masking schemes. These research efforts have led to significant progress in the development of security assessment methodologies and further initiated standardization activities. However, since the majority of this work is theoretical, it is challenging for the more practice-oriented hardware security community to fully grasp and contribute to. To bridge the gap, these advancements are reviewed and discussed in this survey, mainly from the perspective of hardware security. In doing so, a clear taxonomy is provided that is helpful for a systematic treatment of the masking-related topics. By giving an extensive overview of the existing methods, this survey (1) provides a research landscape of circuit masking for newcomers to the field, (2) offers guidelines on which attack model and verification tool to choose when designing masking schemes, and (3) identifies interesting new research directions where masking models and assessment tools can be applied. Thus, this survey serves as an essential reference for hardware security practitioners interested in the theory behind masking techniques, the tools useful to verify the security of masked circuits, and their potential applications.

show abstract

Section: Probing Modelmentioning

confidence: 99%