Level-specific lithography optimization for 1-Gb DRAM

Abstract

A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175-and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography.

Enhanced Design Flow and Optimizations for Multiproject Wafers

“…A number of previous works have proposed techniques 2 Process window is defined as the range of exposure dose and defocus within which acceptable CD tolerance is maintained. to control the forbidden pitches using optimization of optical conditions such as NA and illuminator aperture shape of OAI [11], [20], [21]. All of these works using optimizations of NA and OAI have sought to enlarge the ranges of allowable pitches, as shown in Fig.…”

Introduction to Semiconductor Lithography

“…The common subtractive patterning process (Figure 1.1) involves three steps: (1) deposition of a uniform fi lm of material on the wafer; (2) lithography to create a positive image of the pattern that is desired in the fi lm; and (3) etch to transfer that pattern into the wafer. An additive process (such as electroplating) changes the order of these steps: (1) lithography to create negative image of the pattern that is desired; and (2) selective deposition of material into the areas not protected by the lithographically produced pattern.…”

Through-process modeling in a DfM environment

“…assist feature placement) and OPC; 3 providing a more thorough and rigorous evaluation of real two-dimensional design constructs than previous test pattern based studies. 4 Accurate through-process models can also be extended to process conditions different from where they were calibrated and used to simulate the expected behavior of lithographic tools before they are installed in the fabricator and, in some cases, can reduce the time to bring up a new tool by almost a full OPC cycle. These applications and their model requirements are discussed in Section 2.…”