Leveraging Hardware Message Passing for Efficient Thread Synchronization

Abstract

As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ultimately limited by the performance of the underlying cache coherence protocol. This paper studies how hardware support for message passing can improve synchronization performance. Considering the ubiquitous problem of mutual exclusion, we adapt two stateof-the-art solutions used on shared-memory processors, namely the server approach and the combining approach, to leverage the potential of hardware message passing. We propose HYBCOMB, a novel combining algorithm that uses both message passing and shared memory features of emerging hybrid processors. We also introduce MP-SERVER, a straightforward adaptation of the server approach to hardware message passing. Evaluation on Tilera's TILE-Gx processor shows that MP-SERVER can execute contended critical sections with unprecedented throughput, as stalls related to cache coherence are removed from the critical path. HYB-COMB can achieve comparable performance, while avoiding the need to dedicate server cores. Consequently, our queue and stack implementations, based on MP-SERVER and HYB-COMB, largely outperform their most efficient pure-sharedmemory counterparts.

On the Performance of Delegation over Cache-Coherent Shared Memory

“…In [16], we showed that on a processor provided with hardware message-passing support, such stalls on the server can be fully avoided. Reaching the same result in a cache-coherent sharedmemory system would probably require being able to specify the cache of a remote core where data should be placed, as proposed in [15].…”

“…Elsewhere, we have studied delegation in the context of a processor provided with support for message passing in hardware [16]. The results show that this feature can be used to significantly improve performance, mainly because RMRs on the server's critical path can be fully avoided.…”

“…Their net effect is very dependent on the processor's characteristics: The different RMRs might partially overlap, depending on the memory consistency model of the processor at hand, resulting in fewer CPU stalls. Nevertheless, they remain an important source of overhead even on a processor with weak memory consistency [16]. In the following we study different techniques to minimize their impact on the server performance.…”

“…Delegation is most naturally implemented using message passing, if the hardware at hand provides such a feature [16,19]. This can result in optimal performance, as the server can be fully prevented from stalling [16].…”

“…Delegation is most naturally implemented using message passing, if the hardware at hand provides such a feature [16,19]. This can result in optimal performance, as the server can be fully prevented from stalling [16]. However, many contemporary processors, including the dominant x86 architecture, still do not provide hardware support for message passing, which makes the implementation of delegation much more challenging.…”