Leveraging thermally-aware chiplet organization in 2.5D systems to reclaim dark silicon

Eris, Furkan; Joshi, Ajay; Kahng, Andrew B.; Ma, Yenai; Mojumder, Saiful A.; Zhang, Tiansheng

doi:10.23919/date.2018.8342238

Cited by 19 publications

(17 citation statements)

References 24 publications

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“…This design paradox is referred to as "dark silicon" [201]. In other to overcome these constraints, different approaches are considered such as thermally aware chiplets [202] and balance between fault-tolerance and power consumption [203]. Energy and power consumption is a critical factor for diverse safety-critical systems such as portable medical devices [5] and railway signalling autonomous remote object controllers [137].…”

Section: Energy Power and Thermal Managementmentioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

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Multi-core devices are envisioned to support the development of next-generation safety-critical systems, enabling the on-chip integration of functions of different criticality. This integration provides multiple system-level potential benefits such as cost, size, power, and weight reduction. However, safety certification becomes a challenge and several fundamental safety technical requirements must be addressed, such as temporal and spatial independence, reliability, and diagnostic coverage. This survey provides a categorization and overview at different device abstraction levels (nanoscale, component, and device) of selected key research contributions that support the compliance with these fundamental safety requirements.

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Section: Energy Power and Thermal Managementmentioning

confidence: 99%

Multi-core Devices for Safety-critical Systems

et al. 2020

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“…These works do not consider thermal effects while finding placement and routing solutions. In our prior work [12], we propose a thermallyaware chiplet placement solution. However, our prior work does not perform routing and only computes a placement solution.…”

Section: Related Workmentioning

confidence: 99%

“…Our studies use a 256-core homogeneous (i.e., all cores are of the same type) system. To enable comparisons against the previous literature, we specifically adopt the core design used in our prior work [12]. Cores have the following architectural specifications:…”

Section: 5d System Architecturementioning

confidence: 99%

“…• 18mm × 18mm Total 256-core Chip Area Each core, together with its L1 and L2 caches, has a square layout. Following our prior work [12], we study chiplet-based integration of 16 identical chiplets on an interposer, where each chiplet contains 16 cores. Figure 1 illustrates the cross-section view of a 2.5D system.…”

Section: 5d System Architecturementioning

confidence: 99%

“…In 2.5D design, multiple chiplets are placed on a silicon interposer, and the chiplets communicate using links integrated into the interposer. 2.5D integration technology provides multiple potential benefits compared to 2D systems, including greater system performance within thermal constraints [12], heterogeneous integration of multiple technologies [1,6], and reduced overall system cost [16]. However, 2.5D integration technology also opens up a number of design challenges, ranging from circuit and physical challenges (design and routing of inter-chiplet links, placement and floorplanning of chiplets on the interposer, microbump required for the inter-chiplet links.…”

Section: Introductionmentioning

confidence: 99%

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A cross-layer methodology for design and optimization of networks in 2.5D systems

Coskun

Eris

Joshi

et al. 2018

Proceedings of the International Conference on Computer-Aided Design

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2.5D integration technology is gaining popularity in the design of homogeneous and heterogeneous many-core computing systems. 2.5D network design, both inter-and intra-chiplet, impacts overall system performance as well as its manufacturing cost and thermal feasibility. This paper introduces a cross-layer methodology for designing networks in 2.5D systems. We optimize the network design and chiplet placement jointly across logical, physical, and circuit layers to achieve an energy-efficient network, while maximizing system performance, minimizing manufacturing cost, and adhering to thermal constraints. In the logical layer, our cooptimization considers eight different network topologies. In the physical layer, we consider routing, microbump assignment, and microbump pitch constraints to account for the extra costs associated with microbump utilization in the inter-chiplet communication. In the circuit layer, we consider both passive and active links with five different link types, including a gas station link design. Using our cross-layer methodology results in more accurate determination of (superior) inter-chiplet network and 2.5D system designs compared to prior methods. Compared to 2D systems, our approach achieves 29% better performance with the same manufacturing cost, or 25% lower cost with the same performance.

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