LFSR based fast seed selection technique reducing test time of I<sub>DDQ</sub> testing

Islam, Shabiul; Jidin, Razali; Ali, Mohd

doi:10.1109/isiea.2009.5356430

Cited by 1 publication

(1 citation statement)

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“…This also has the disadvantage of employing expensive communication infrastructure for the test data which can negatively affect the performance of the system. Many works have been done for improving LFSR based BIST architectures [12][13][14], LFSR reconfiguration [15], and optimized reseeding [16][17][18] to get high fault coverage and less test application time. In order to achieve high fault coverage alongside with low test application time, some works [8][9][10][11] have attempted to use hybrid BIST methods that include scan based approaches.…”

Section: Introductionmentioning

confidence: 99%

BILBO-friendly hybrid BIST architecture with asymmetric polynomial reseeding

Sadredini

Najafi

Navabi

2012

The 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS 2012)

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Abstract-By advances in technology, integrated circuits have come to include more functionality and more complexity in a single chip. Although methods of testing have improved, but the increase in complexity of circuits, keeps testing a challenging problem. Two important challenges in testing of digital circuits are test time and accessing the circuit under test (CUT) for testing. These challenges become even more important in complex system on chip (SoC) zone. This paper presents a multistage test strategy to be implemented on a BIST architecture for reducing test time of a simple core as solution for more global application of SoC testing strategy. This strategy implements its test pattern generation and output response analyzer in a BILBO architecture. The proposed method benefits from an irregular polynomial BILBO (IP-BILBO) structure to improve its test results. Experimental results on ISCAS-89 benchmark circuits show an average of 35% improvement in test time in proportion to pervious work.

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