LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs

Abstract

The paper discusses possibilities of rearranging test decompressor internal structure and linking its outputs with the parallel scan chain inputs in order to obtain better compression efficiency while the hardware overhead is not increased. We have experimentally verified that the controllability of decompressor outputs can be used as a simple and easily computable measure of the decompressor efficiency. Based on this observation we have developed a procedure that chooses a suboptimal LFSR outputs and parallel scan chain inputs interconnection. The procedure proposes a permutation of the scan chain inputs so that the scan chains that are fed with patterns with higher number of care bits are linked with the highly controllable decompressor outputs. We have experimentally verified on the benchmark circuits that adopting the proposed strategy improves the compression efficiency. Keywords-Design for testability (DFT), scan-based test, linear finite state machines, manufacturing test, test application time reduction, test data volume compression.

Horizontal diversity in test generation for high fault coverage

“…Speedy testing even throughout the production cycle is not sufficient to maintain modern reliability standards [8]. Therefore, high performance embedded systems are equipped with highly reliable built-in self-test (BIST) for an on-chip testing during normal operations [9][10][11][12][13][14]. Comprising of test pattern generator and output response analyzer within the system, BIST automatically generates test patterns and compares the fault-free responses [10][11][12][13]15].…”

“…BIST uses pseudorandom test pattern generation (PRTG) through linear feedback shift register (LFSR) because of its simplicity and cost effectiveness [3,9,[11][12][13][16][17][18]. PRTG outperforms other black-box test pattern generation approaches with its ability to generate large number of random test patterns irrespective of the structural implementation of circuit under test (CUT) [19].…”