2021
DOI: 10.1109/access.2021.3103200
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Lifetime Reliability Improvement of Nano-Scale Digital Circuits Using Dual Threshold Voltage Assignment

Abstract: In nano-scale CMOS technology, circuit reliability is a growing concern for complicated digital circuits due to manufacturing process variation and aging effects. In this paper, a statistical circuit optimization framework is presented to analyze and improve the lifetime reliability of digital circuits in the presence of process variation and aging degradation. The proposed framework takes advantage of a process variation-and aging-aware gate-level delay degradation model to characterize and evaluate the lifet… Show more

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Cited by 4 publications
(1 citation statement)
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“…In scheduled voltage scaling, the voltage increases gradually at runtime and has the potential to increase IC lifetime by about 45%. In the state-of-the-art study of [159], a statistical optimization framework is presented to improve the lifetime resilience of digital circuits in the presence of aging degradation based on the gate-level delay degradation model. Here, to estimate a criticality metric, a set of statistically optimized critical gates is selected.…”
Section: ) Voltage Adaptationmentioning
confidence: 99%
“…In scheduled voltage scaling, the voltage increases gradually at runtime and has the potential to increase IC lifetime by about 45%. In the state-of-the-art study of [159], a statistical optimization framework is presented to improve the lifetime resilience of digital circuits in the presence of aging degradation based on the gate-level delay degradation model. Here, to estimate a criticality metric, a set of statistically optimized critical gates is selected.…”
Section: ) Voltage Adaptationmentioning
confidence: 99%