Lightweight Architecture for Elliptic Curve Scalar Multiplication over Prime Field

Abstract

In this paper, we present a novel lightweight elliptic curve scalar multiplication architecture for random Weierstrass curves over prime field Fp. The elliptic curve scalar multiplication is executed in Jacobian coordinates based on the Montgomery ladder algorithm with (X,Y)-only common Z coordinate arithmetic. At the finite field operation level, the adder-based modular multiplier and modular divider are optimized by the pre-calculation method to reduce the critical path while maintaining low resource consumption. At the group operation level, the point addition and point doubling methods in (X,Y)-only common Z coordinate arithmetic are modified to improve computation parallelism. A compact scheduling method is presented to improve the architecture’s performance, which includes appropriate scheduling of finite field operations and specific register connections. Compared with existing works, our design is implemented on the FPGA platform without using DSPs or BRAMs for higher portability. It utilizes 6.4k~6.5k slices in Kintex-7, Virtex-7, and ZYNQ FPGA and executes an elliptic curve scalar multiplication for a field size of 256-bit in 1.73 ms, 1.70 ms, and 1.80 ms, respectively. Additionally, our design is resistant to timing attacks, simple power analysis attacks, and safe-error attacks. This architecture outperforms most state-of-the-art lightweight designs in terms of area-time products.

Area‐time efficient point multiplication architecture on twisted Edwards curve over general prime field GF(p)

“…The area–time product (NATP) of our design is better than all the designs listed in Table 5 and Figure 4. It has 2.2 , 1.8 , 2.4 , 13.2 , 3.2 , 4.4 , 6.8 , 5.3 , 3.1 , 2.5 , 3.4 , 2.94 , and 2.3 better NATP as compared to previous works, 23–26,28–35,54 respectively. Awaludin et al's design 27 is the only design with almost the same NATP value; however, it is based on embedded FPGA blocks (DSPs + BRAMs) so our design is more flexible than Awaludin et al's design 27 .…”

“…In terms of efficiency, the proposed ECSM design is better than all the discussed designs as evident by the figure. To be precise, it has 2.3 , 1.7 , 2.5 , 13.3 , 3.2 , 4.5 , 6.9 , 5.3 , 3.1 , 2.5 , 3.3 , 3 , and 2.94 higher efficiency as compared to previous works, 23–26,28–35,54 respectively. Note that only Awaludin et al 27 is the only design with similar efficiency and NATP values; however, it heavily relies on DSP blocks and BRAMs.…”

“…In detail, the hardware resource consumption of the proposed ECSM architecture on Virtex‐7 FPGA is given in Table 6. Hao et al 30 proposed a lightweight ECC implementation of ECSM over a general prime field using common‐ coordinates. The implementation results on Virtex‐7 FPGA were presented for key lengths 160–256 bits.…”

“…Hardware acceleration of ECSM using the FPGA platform has been researched extensively in recent years. Several high‐performance and compact ECSM hardware architectures have been proposed 23–40 . In previous works, 33,39 ECC implementations are developed over the twisted Edwards curve, whereas all other ECC implementations utilized the Weirstrass curve.…”

“…Several high-performance and compact ECSM hardware architectures have been proposed. [23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40] In previous works, 33,39 ECC implementations are developed over the twisted Edwards curve, whereas all other ECC implementations utilized the Weirstrass curve. Islam et al 33 proposed a high-performance ECC co-processor exploiting unified point addition over twisted Edwards curves.…”