Lightweight Authenticated Encryption for Network-on-Chip Communications

Harttung, Julian; Franz, Elke; Moriam, Sadia; Walther, Paul

doi:10.1145/3299874.3317990

Cited by 6 publications

(3 citation statements)

References 19 publications

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“…Another possible topic for future work could be the investigation of the proposed schemes using different cryptographic primitives. A promising contender can be PRINCE [34] as proposed in [35]. Its main advantage is the performance of 1 cycle per block, which would significantly reduce the latency of the current solution.…”

Section: Discussionmentioning

confidence: 99%

Efficient Communication Protection of Many-Core Systems against Active Attackers

et al. 2021

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Many-core system-on-chips, together with their established communication infrastructures, Networks-on-Chip (NoC), are growing in complexity, which encourages the integration of third-party components to simplify and accelerate production processes. However, this also adversely exposes the surface for attacks through the injection of hardware Trojans. This work addresses active attacks on NoCs and focuses on the integrity and availability of transmitted data. In particular, we consider the modification and/or dropping of data during transmission as active attacks that might be performed by malicious routers. To mitigate the impact of such active attacks, we propose two lightweight solutions that respect the performance constraints of NoCs. Assuming the presence of symmetric keys, these approaches combine lightweight authentication codes for integrity protection with network coding for increased efficiency and robustness. The proposed solutions prevent undetected modifications and significantly increase availability through a reliable detection of attacks. The efficiency of these solutions is investigated in different scenarios using cycle-accurate simulations and the area overhead is analyzed relative to state-of-the-art many-core system. The results demonstrate that one authentication scheme with network coding protects the integrity of data to a low residual error of 1.36% at 0.2 attack probability with an area overhead of 2.68%. For faster and more flexible evaluation, an analytical approach is developed which is validated against the cycle-accurate simulations. The analytical approach is more than 1000× faster while having a maximum estimation error of 5%. Moreover, the analytical model provides a deeper insight into the system’s behavior. For example, it reveals which factors influence the performance parameters.

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Section: Discussionmentioning

confidence: 99%

Efficient Communication Protection of Many-Core Systems against Active Attackers

et al. 2021

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“…In EETD: An Energy Efficient Design for Runtime Hardware Trojan Detection [14], a security structure for NoC based architectures is proposed wherein he work combined encryption, authentication, and network coding methods. The proposed scheme primarily focuses on restricting the unauthorised access to important information contained inside a secure core.…”

Section: Related Workmentioning

confidence: 99%

Hardware Trojan Detection and Mitigation in NoC using Key authentication and Obfuscation Techniques

et al. 2022

EMITTER Int'l J. of Engin. Technol.

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Today's Multiprocessor System-on-Chip (MPSoC) contains many cores and integrated circuits. Due to the current requirements of communication, we make use of Network-on-Chip (NoC) to obtain high throughput and low latency. NoC is a communication architecture used in the processor cores to transfer data from source to destination through several nodes. Since NoC deals with on-chip interconnection for data transmission, it will be a good prey for data leakage and other security attacks. One such way of attacking is done by a third-party vendor introducing Hardware Trojans (HTs) into routers of NoC architecture. This can cause packets to traverse in wrong paths, leak/extract information and cause Denial-of-Service (DoS) degrading the system performance. In this paper, a novel HT detection and mitigation approach using obfuscation and key-based authentication technique is proposed. The proposed technique prevents any illegal transitions between routers thereby protecting data from malicious activities, such as packet misrouting and information leakage. The proposed technique is evaluated on a 4x4 NoC architecture under synthetic traffic pattern and benchmarks, the hardware model is synthesized in Cadence Tool with 90nm technology. The introduced Hardware Trojan affects 8% of packets passing through infected router. Experimental results demonstrate that the proposed technique prevents those 10-15% of packets infected from the HT effect. Our proposed work has negligible power and area overhead of 8.6% and 2% respectively.

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“…NoC is used for routing between multiple cores as NoC is a flexible, scalable, and efficient interconnection technique [1], [2]. NoC can be used in many applications, such as processing components of an aircraft [3], [4] and processors in computers [5]- [8]. Apart from providing efficient communication, NoCs are expected to be power efficient [9], [10] and ideally free of fault and failures.…”

Section: Introductionmentioning

confidence: 99%

Self-Healing Router Approach for High-Performance Network-on-Chip

Khalil

Eldash

Kumar

et al. 2021

IEEE Open J. Circuits Syst.

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Network-on-Chip (NoC) is used as the communication network in many applications that use multiple cores or Processing Elements (PEs). Routers play a crucial role as connectors since a faulty router can degrade the NoC's performance and cause miscommunication between the network's components. Thus a faulty router may cause the system to fail. To avoid failure in routers in NoCs, a novel self-healing technique is proposed. Self-healing serves to recover hardware faults, and it is defined as the ability of a system to recover from its faults without any external intervention. The proposed self-healing method is to heal faulty routers and their port buffers of faults as they occur. The proposed method uses the neighboring routers of a faulty router for computation. The data packet includes three bits for routing. A neighbor's active router updates these bits according to the destination of the packet. A self-healing block is added inside each router. The proposed method also covers faulty buffers, and it uses active buffers to store the packet of a faulty one. It has been implemented and tested using VHDL and Altera Arria 10 GX FPGA. It has been found to attain improved reliability and Mean Time to Failure (MTTF) at an area overhead of 27%. It has been tested for complex NoC structure, and the results show it is practical, scalable, stable, and robust.INDEX TERMS NoC, self-healing, hardware faults, fault tolerance, neural network, FPGA architecture.

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Lightweight Authenticated Encryption for Network-on-Chip Communications

Cited by 6 publications

References 19 publications

Efficient Communication Protection of Many-Core Systems against Active Attackers

Efficient Communication Protection of Many-Core Systems against Active Attackers

Hardware Trojan Detection and Mitigation in NoC using Key authentication and Obfuscation Techniques

Self-Healing Router Approach for High-Performance Network-on-Chip

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