Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Abstract

Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Compared to its predecessor, VVC introduces new coding tools to make compression more efficient at the expense of higher computational complexity. This rises a need to design an efficient and optimised implementation especially for embedded platforms with limited memory and logic resources. One of the newly introduced tools in VVC is the Multiple Transform Selection (MTS). This latter involves three Discrete Cosine Transform (DCT)/Discrete Sine Transform (DST) types with larger and rectangular transform blocks. In this paper, an efficient hardware implementation of all DCT/DST transform types and sizes is proposed. The proposed design uses 32 multipliers in a pipelined architecture which targets an ASIC platform. It consists in a multi-standard architecture that supports the transform block of recent MPEG standards including AVC, HEVC and VVC. The architecture is optimized and removes unnecessary complexities found in other proposed architectures by using regular multipliers instead of multiple constant multipliers. The synthesized results show that the proposed method which sustain a constant throughput of two pixels/cycle and constant latency for all block sizes can reach an operational frequency of 600 Mhz enabling to decode in real-time 4K videos at 48 fps.

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design

“…The works [78]- [85] present hardware architectures for the VVC transform module considering the encoder and decoder systems. In these works, different hardware technologies and different approaches were considered to implement the forward and inverse transforms.…”

“…In these works, different hardware technologies and different approaches were considered to implement the forward and inverse transforms. From these papers, we selected to discuss the works [83] and [85], since one solution targets the decoder and other targets the encoder and both targeted ASIC technologies and used the newest reference software versions among the related works, Fan et al [83] proposed a high-performance pipelined hardware implementation for 2D DST-VII/DCT-VIII transform operations in VVC. The developed hardware architecture considers square and rectangular-shaped block sizes, except 64×64 block size.…”

“…Farhat et al [85] developed a hardware architecture for the transform module of the VVC decoder. The hardware architecture supports 1D Inverse DCT-II (IDCT-II) and IDST-VII/IDCT-VIII with sizes ranging from 4 to 64 and from 4 to 32, respectively.…”

Modern Video Coding: Methods, Challenges and Systems

“…As in AV1, VVC presents a secondary transform called low frenquency non-separable transform (LFNST), which is only applied over 4x4 or 8x8 blocks. At the moment, there are a few works found in the literature with hardware proposals for the transform and quantization modules of this standard, such as [60], [61], and [62].…”

A Novel Information Hiding Method for H.266/VVC Based on Selections of Luminance Transform and Chrominance Prediction Modes

“…For the intra prediction, H.266/VVC introduces several new mechanisms [25], such as Matrix weighted Intra Prediction (MIP) [26], Multiple reference line (MRL) [27], and Crosscomponent linear model (CCLM) [28], which increases the flexibility of mode selection, thus potentially suiting information hiding. Further, H.266/VVC designs a novel adaptive transform selection mechanism, named Multiple Transform Selection (MTS) [29], to switch between horizontal and vertical residual transforms based on the hybrid DCT+DST scheme and make the compression more effective. This provides further flexibility for information hiding.…”