Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration

Ioannou, Lenos; Fahmy, Suhaib A.

doi:10.1109/icfpt47387.2019.00066

Cited by 2 publications

(2 citation statements)

References 9 publications

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“…Architecture centric overlays were shown to ofer high throughput since they utilize the underlying FPGA resources more eiciently [30]. The work in [31] described a streaming overlay for fully connected layers utilizing the DSP blocks of a Zynq Ultrascale+ ZU7EV FPGA. That design was shown to achieve close to the theoretical maximum frequency while using minimal resources, but supported only feed-forward networks with the ReLU activation function, and was not shown to scale.…”

Section: Related Workmentioning

confidence: 99%

Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs

Ioannou

Fahmy

2022

ACM Trans. Reconfigurable Technol. Syst.

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Long-Short Term Memory (LSTM) networks, and Recurrent Neural Networks (RNNs) in general, have demonstrated their suitability in many time series data applications, especially in Natural Language Processing (NLP). Computationally, LSTMs introduce dependencies on previous outputs in each layer that complicate their computation and the design of custom computing architectures, compared to traditional feed-forward networks. Most neural network acceleration work has focused on optimising the core matrix-vector operations on highly capable FPGAs in server environments. Research that considers the embedded domain has often been unsuitable for streaming inference, relying heavily on batch processing to achieve high throughput. Moreover, many existing accelerator architectures have not focused on fully exploiting the underlying FPGA architecture, resulting in designs that achieve lower operating frequencies than the theoretical maximum. This paper presents a flexible overlay architecture for LSTMs on FPGA SoCs that is built around a streaming dataflow arrangement, uses DSP block capabilities directly, and is tailored to keep parameters within the architecture while moving input data serially to mitigate external memory access overheads. The architecture is designed as an overlay that can be configured to implement alternative models or update model parameters at runtime. It achieves higher operating frequency and demonstrates higher performance than other lightweight LSTM accelerators, as demonstrated in an FPGA SoC implementation.

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Section: Related Workmentioning

confidence: 99%

Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs

Ioannou

Fahmy

2022

ACM Trans. Reconfigurable Technol. Syst.

Self Cite

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“…Ioannou and Fahmy 36 propose a lightweight streaming neural network overlay at RTL-level for FC-ANN models created for the Iris, Diabetes and Customer churn data sets by efficiently taking advantage of DSP blocks, which achieve a frequency which is close to the theoretical maximum frequency of the platform.…”

Section: Function-level Parallelism In Fc-ann Via Hlsmentioning

confidence: 99%

Deep reinforcement learning‐based autonomous parking design with neural network compute accelerators

Özeloğlu

Gürbüz

San

2021

Concurrency and Computation

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We describe the design and implementation of an autonomous prototype vehicle which finds an empty parking slot in a parking area, and parks itself in the empty parking slot, using neural networks based on deep reinforcement learning (RL). To perform an autonomous parking procedure for our prototype vehicle, two different artificial neural networks (ANNs) are trained using a deep RL Algorithm in a simulation environment and embedded into the computing platform of the prototype car.One of the ANNs enables the vehicle to drive autonomously in the parking environment. At the same time, an image processing algorithm is used to determine whether a parking slot is empty. When the image processing algorithm finds a suitable parking slot, a different ANN is activated and performs a safe parking procedure. However, ANN-based machine learning techniques require high processing power and impose a high computational burden on embedded CPU and GPU platforms. To alleviate the computational burden, one can achieve higher performance and less power consumption using an application-specific hardware design, where logic resources are fully exploited according to the algorithm of interest, in an energy-efficient manner. In this article, hardware accelerators for our ANN models are designed and generated via the Vivado high-level synthesis (HLS) tool, targeting an ARM based programmable SoC platform, ZedBoard. Our ANN accelerators have achieved a speedup of 17x as compared to an ARM software implementation. For deeper fully-connected layers used in deep RL-based solutions, function-level parallelism (Vivado's dataflow) is employed to improve the computational efficiency. Our proposed stage-level description for fully connected layers outperforms recent studies in terms of computation time.

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Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration

Abstract: Please refer to published version for the most recent bibliographic citation information. If a published version is known of, the repository item page linked to above, will contain details on accessing it.

Cited by 2 publications

References 9 publications

Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs

Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs

Deep reinforcement learning‐based autonomous parking design with neural network compute accelerators

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