Lightweight Side-Channel Protection using Dynamic Clock Randomization

Hettwer, Benjamin; Das, Kallyan; Leger, Sebastien; Gehrer, Stefan; Güneysu, Tim

doi:10.1109/fpl50879.2020.00041

Cited by 24 publications

(7 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Additionally, small batch sizes have an intrinsic influence on regularisation and can be as a result of noise effects in the learning process. A very low learning rate (0.001 or less) is required for very small batch sizes to maintain stability [21].…”

Section: Training Accuracymentioning

confidence: 99%

Deep Learning Method for Power Side-Channel Analysis on Chip Leakages

Ahmed,

Salim,

Hasan

2023

ELEKTRON ELEKTROTECH

View full text Add to dashboard Cite

Power side channel analysis signal analysis is automated using deep learning. Signal processing and cryptanalytic techniques are necessary components of power side channel analysis. Chip leakages can be found using a classification approach called deep learning. In addition to this, we do this so that the deep learning network can automatically tackle signal processing difficulties such as re-alignment and noise reduction. We were able to break minimally protected Advanced Encryption Standard (AES), as well as masking-countermeasure AES and protected elliptic-curve cryptography (ECC). These results demonstrate that the attacker knowledge required for side channel analysis, which had previously placed a significant emphasis on human abilities, is decreasing. This research will appeal to individuals with a technical background who have an interest in deep learning, side channel analysis, and security.

show abstract

Section: Training Accuracymentioning

confidence: 99%

Deep Learning Method for Power Side-Channel Analysis on Chip Leakages

Ahmed,

Salim,

Hasan

2023

ELEKTRON ELEKTROTECH

View full text Add to dashboard Cite

show abstract

“…Due to their nature, such attacks take the name Side-Channel Attacks (SCAs), and Figure 3 SCAs are widely documented in the literature and constitute one of the hottest topics in the cybersecurity field. An exhaustive and systematic review of SCAs can be found in [44][45][46], while [47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63] report several examples of the most diffused categories of attacks that exploit the physical implementation of a device, which are listed below:…”

Section: Rotmentioning

confidence: 99%

“…Power analysis [53][54][55][56][57][58][59][60][61]64,65]: This family of attacks is one of the most effective on both hardware and software implementations, and it exploits the power consumption of underlying physical circuits. Concerning the software case, if each opcode of the instruction set architecture can be associated with a different and specific power trace shape, then the series of operations performed by a routine is revealed; on the hardware side, data dependencies over different power traces can be analyzed to recover secret information.…”

mentioning

confidence: 99%

Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments

Crocetti,

Nannipieri,

Di Matteo

et al. 2023

Electronics

View full text Add to dashboard Cite

Cyberattacks and cybercriminal activities constitute one of the biggest threats in the modern digital era, and the frequency, efficiency, and severity of attacks have grown over the years. Designers and producers of digital systems try to counteract such issues by exploiting increasingly robust and advanced security mechanisms to provide secure execution environments aimed at preventing cyberattacks or, in the worst case, at containing intrusions by isolation. One of the most significative examples comes from General Purpose Processor (GPP) manufacturers such as Intel, AMD, and ARM, which in the last years adopted the integration of dedicated resources to provide Trusted Execution Environments (TEEs) or secure zones. TEEs are built layer by layer on top of an implicitly trusted component, the Root-of-Trust (RoT). Since each security chain is only as strong as its weakest link, each element involved in the construction of a TEE starting from the RoT must be bulletproof as much as possible. In this work, we revise and propose a design methodology to implement in both hardware (HW) and software (SW) highly featured and robust security blocks by highlighting the key points that designers should take care of, and the key metrics that should be used to evaluate the security level of the developed modules. We also include an analysis of the state of the art concerning RoT-based TEEs, and we illustrate a case study that documents the implementation of a cryptographic coprocessor for the secure subsystem of the Rhea GPP from the European Processor Initiative (EPI) project, according to the presented methodology. This work can be used by HW/SW security module designers as a cutting-edge guideline.

show abstract

“…The frequency of the clock signal directly influences the power dissipation of a circuit. Thus, several works in the literature explore this strategy in different ways as recently Jayasinghe et al [56], Hettwer et al [57]. These approaches exploit the configurable clock management available in FPGAs to dynamically generate clock signals with a large frequency spectrum.…”

Section: B Hiding: Random Consumptionmentioning

confidence: 99%

Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present

Soares

Lima

Lellis

et al. 2021

JICS

View full text Add to dashboard Cite

Modern cryptographic circuits are increasingly demanding security requirements. Since its invention, power analysis attacks are a threat to the security of such circuits. In order to contribute to the design of secure circuits, designers may employ countermeasures in different abstraction levels. This work presents a brief survey of countermeasures to help designers to find good solutions for the design of secure cryptographic systems. A summary is highlighted to compare the pros and cons of the approaches to help designers choose a better solution, or even provide subsidies so that new solutions can be proposed.

show abstract

Lightweight Side-Channel Protection using Dynamic Clock Randomization

Cited by 24 publications

References 16 publications

Deep Learning Method for Power Side-Channel Analysis on Chip Leakages

Deep Learning Method for Power Side-Channel Analysis on Chip Leakages

Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments

Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present

Contact Info

Product

Resources

About