Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications

Houri, Samer; Billiot, G.; Belleville, Marc; Valentian, Alexandre; Fanet, Hervé

doi:10.1109/tcsi.2015.2415177

Cited by 42 publications

(32 citation statements)

References 23 publications

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“…By combining the dissipation expressions obtained for the NEM relays with those of the generators it is possible to estimate the optimum operating frequencies and minimum dissipated These optimal values are summarized in Table 1 along with those obtained in [13] for the LC generator. Furthermore, the performance of the different NEM-generator combinations are plotted in Fig.…”

Section: Discussionmentioning

confidence: 99%

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Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits

Houri

Billiot

Belleville

et al. 2015

Reversible Computation

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Abstract. The influence of the power-clock generator on the global energyperformance relationship of nanoelectromechanical (NEM) switch-based quasi-adiabatic logic circuits is investigated in this paper. This investigation is undertaken the capacitor bank type generator, it is found that the leakage current of the MOSFET switching devices used within the generator constitutes an important source of performance degradation. Capacitor type generators are found to be most efficient for low operating frequencies (less than a MHz). Keywords:Power-clock generator · Adiabatic charging · Adiabatic logic · Quasi-adiabatic logic · Nanoelectromechanical relays IntroductionAlthough reversible and adiabatic computing, that can be traced back to [1], is an interesting approach to low power energy efficient computing, solutions based on this approach have yet to gain wide adoption. This is in part due to the introduced complexity overhead in the case of reversible and adiabatic logic [2,3], but also due to the fact that MOSFET devices are simply not well suited to fully apply such circuits. This fact stems from limitations that are inherent to MOSFET devices, mainly their leakage and low gradient subthreshold slope. If these two issues are circumvented, then reversible and quasi-adiabatic logic become more energy efficient when compared to other available alternatives such as subthreshold logic. And while advanced semiconductor-based solutions are able to promise improvements on current MOSFET performance, such as in the case of finFETs [4] and tunnel FETs [5], these solutions remain limited by the semiconductor physics itself. Therefore, metal-insulator type combinations are being pursued instead of semiconducting ones, this approach explains the recent revival in interest in mechanical relay type switches, albeit at the nanoscale [6-10], thus nanoelectromechanical (NEM) switches are a promising and viable candidate to replace MOSFET

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Section: Discussionmentioning

confidence: 99%

“…explored NEM-based quasi-adiabatic logic and repor ttention was given to the question of the necessary ramp wer-clock, necessary for quasi-adiabatic logic circuits se when a power-clock generator-NEM quasi-adiabatic lo [13], it was found that the generator constitutes a limit potential that accompanies the use of NEM switches.…”

Section: Introductionmentioning

confidence: 99%

Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits

Houri

Billiot

Belleville

et al. 2015

Reversible Computation

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“…These devices introduce non-adiabatic losses which detriment overall energy efficiency of adiabatic logic. Additionally, frequency achieved in adiabatic circuits is far lower than in conventional CMOS logic [6,7].…”

Section: Introductionmentioning

confidence: 97%

“…Current advancements in integration technology and novel devices have brought again interest on adiabatic logic. Novel devices such as nano-electro-mechanical switches (NEMS), carbo nanotube based field effect transistors (CNTFETs) or vertical slit field effect transistors (VESFETs) are potential replacements of MOSFETS to further reduce nonadiabatic energy dissipation and achieve higher switching frequencies [7,8]. Thanks to these novel switches, the adiabatic logic may be a promising alternative for ultra-low power circuit design.…”

Section: Introductionmentioning

confidence: 99%

Investigation of the power-clock network impact on adiabatic logic

Jeanniot

Todri‐Sanial

Nouet

et al. 2016

2016 IEEE 20th Workshop on Signal and Power Integrity (SPI)

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Abstract-Adiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the powerclock network still remains to be studied. In this paper, we investigate the power-clock network effect on adiabatic energy dissipation. We derive closed-form analytical formulas to represent the output signal voltage and energy dissipation while taking into account the parasitic impedance of the power-clock network with respect to switching frequency such that adiabatic conditions are still met. Experiments, based on simulation, show that the power-clock network impacts both the energy efficiency of the circuit and its frequency.

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“…The continuous-time fully-differential modulator topology will further prevent these supply noise aggressors from being aliased in-band during sampling. The system clock of 1.69 MHz is directly extracted from the resonant tank using adiabatic logic [22] and down-converted using a series of frequency dividers.…”

Section: Introductionmentioning

confidence: 99%

Autonomous SoC for Neural Local Field Potential Recording in mm-Scale Wireless Implants

Leene

Maslik

Feng

et al. 2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ∆Σ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 µm CMOS technology allowing for waferscale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77µVrms. The resulting electronics has a core area of 2.1 mm 2 and a power budget of 92 µW.

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Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications

Cited by 42 publications

References 23 publications

Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits

Power-Clock Generator Impact on the Performance of NEM-Based Quasi-Adiabatic Logic Circuits

Investigation of the power-clock network impact on adiabatic logic

Autonomous SoC for Neural Local Field Potential Recording in mm-Scale Wireless Implants

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